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TPS54312MPWPREP Datasheet(PDF) 2 Page - Texas Instruments

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Part # TPS54312MPWPREP
Description  3-V TO 6-V INPUT, 3-A OUTPUT SYNCHRONOUS-BUCK PWM SWITCHER WITH INTEGRATED FETs (SWIFT??
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TPS54312MPWPREP Datasheet(HTML) 2 Page - Texas Instruments

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TPS54311-EP, TPS54312-EP,
TPS54313-EP, TPS54314-EP,
TPS54315-EP, TPS54316-EP
SGLS376A – FEBRUARY 2007 – REVISED MARCH 2007
The TPS54311, TPS54312, TPS54313, TPS54314, TPS54315 and TPS54316 devices are available in a
thermally enhanced 20-pin TSSOP (PWP) PowerPAD™ package, which eliminates bulky heatsinks. Texas
Instruments provides evaluation modules and the SWIFT designer software tool to aid in quickly achieving
high-performance power supply designs to meet aggressive equipment development cycles.
ORDERING INFORMATION(1)
TJ
OUTPUT VOLTAGE
PACKAGED DEVICES PLASTIC HTSSOP
TOP SIDE MARKING
(PWP)(2)
0.9 V
TPS54311MPWPREP
TPS54311
1.2 V
TPS54312MPWPREP
TPS54312
1.5 V
TPS54313MPWPREP
TPS54313
–55
°C to 125°C
1.8 V
TPS54314MPWPREP
TPS54314
2.5 V
TPS54315MPWPREP
TPS54315
3.3 V
TPS54316MPWPREP
TPS54316
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2)
The PWP package is taped and reeled as indicated by the R suffix. See application section of data sheet for PowerPAD drawing and
layout information
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
NO.
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT
AGND
1
resistor and FSEL pin. Make PowerPAD connection to AGND.
Bootstrap input. 0.022-
µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for
BOOT
5
the high-side FET driver.
FSEL
19
Frequency select input. Provides logic input to select between two internally set switching frequencies.
NC
3
No connection
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper
PGND
11–13
areas to the input and output supply returns, and negative terminals of the input and output capacitors.
PH
6–10
Phase input/output. Junction of the internal high and low-side power MOSFETs, and output inductor.
Power good open drain output. Hi-Z when VSENSE
≥ 90% V
ref, otherwise PWRGD is low. Note that output is low
PWRGD
4
when SS/ENA is low or internal shutdown signal active.
RT
20
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency, fs.
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
SS/ENA
18
capacitor input to externally set the start-up time.
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with
VBIAS
17
a high quality, low ESR 0.1-
µF to 1-µF ceramic capacitor.
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to
VIN
14–16
device package with a high quality, low ESR 1-
µF to 10-µF ceramic capacitor.
VSENSE
2
Error amplifier inverting input. Connect directly to output voltage sense point.
2
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