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Power Good (PWRGD)

T

delay +

1000

ƒ

s(kHz)

ms

(5)

Bias Voltage (VBIAS)

Bootstrap Voltage (BOOT)

Error Amplifier

Voltage Reference

PWM Control and Feed Forward

TPS54350-EP

SGLS308 – OCTOBER 2005

The VSENSE pin is compared to an internal reference signal, if the VSENSE is greater than 97% and no other

faults are present, the PWRGD pin presents a high impedance. A low on the PWRGD pin indicates a fault. The

PWRGD pin has been designed to provide a weak pulldown and indicates a fault even when the device is

unpowered. If the TPS54350 has power and has any fault flag set, the TPS54350 indicates the power is not

good by driving the PWRGD pin low. The following events, singly or in combination, indicate power is not good:

•

VSENSE pin out of bounds

•

Overcurrent

•

Thermal shutdown

•

UVLO undervoltage

•

Input voltage not present (weak pull down)

•

Slow starting

•

VBIAS voltage is low

Once the PWRGD pin presents a high impedance (i.e., power is good), a VSENSE pin out of bounds condition

forces PWRGD pin low (i.e., power is bad) after a time delay. This time delay is a function of the switching

The VBIAS regulator provides a stable supply for the internal analog circuits and the low side gate driver. Up to 1

mA of current can be drawn for use in an external application circuit. The VBIAS pin must have a bypass

capacitor value of 1 µF. X7R or X5R grade dielectric ceramic capacitors are recommended because of their

stable characteristics over temperature.

The BOOT capacitor obtains its charge cycle by cycle from the VBIAS capacitor. A capacitor from the BOOT pin

to the PH pins is required for operation. The bootstrap connection for the high side driver must have a bypass

capacitor of 0.1 µF.

The VSENSE pin is the error amplifier inverting input. The error amplifier is a true voltage amplifier with 1.5 mA

of drive capability with a minimum of 60 dB of open loop voltage gain and a unity gain bandwidth of 2 MHz.

The voltage reference system produces a precision reference signal by scaling the output of a temperature

stable bandgap circuit. During production testing, the bandgap and scaling circuits are trimmed to produce 0.891

V at the output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure

improves the regulation, since it cancels offset errors in the scaling and error amplifier circuits.

Signals from the error amplifier output, oscillator, and current limit circuit are processed by the PWM control logic.

Referring to the internal block diagram, the control logic includes the PWM comparator, PWM latch, and the

adaptive dead-time control logic. During steady-state operation below the current limit threshold, the PWM

comparator output and oscillator pulse train alternately reset and set the PWM latch.

Once the PWM latch is reset, the low-side driver and integrated pulldown MOSFET remain on for a minimum

duration set by the oscillator pulse width. During this period, the PWM ramp discharges rapidly to the valley

voltage. When the ramp begins to charge back up, the low-side driver turns off and the high-side FET turns on.

The peak PWM ramp voltage varies inversely with input voltage to maintain a constant modulator and power

stage gain of 8 V/V.

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