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TPS65100-Q1 Datasheet(PDF) 2 Page - Texas Instruments |
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TPS65100-Q1 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 27 page VIN COMP VCOMIN EN ENR C1+ C1− DRV FB2 REF FB4 BASE SW SW FB1 SUP C2+ C2−/MODE OUT3 FB3 VCOM PGND PGND GND TPS65100 D1 C3 Vo3 up to 30 V/20 mA C7 C8 C10 Q1 BCP68 D2 D3 C1 R3 R4 C11 C6 C9 R5 R6 C4 C2 C5 R2 R1 C12 C11 10 nF R7 R8 VI 2.7 to 5.8 V 22 µF L1 4.7 µH VO1 Up to 15 V/350 mA VO1 0.22 µF 0.22 µF 0.22 µF VO2 Up to 12 V/20 mA 220 nF VI 1 µF 4.7 µF VO4 3.3 V 0.22 µF 22 µF 0.22 µF Vcom 1 µF TPS65100-Q1 SLVS849A – JULY 2008 – REVISED APRIL 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. TYPICAL APPLICATION CIRCUIT ORDERING INFORMATION(1) TA PACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING –40°C to 125°C TSSOP – PWP Reel of 2000 TPS65100QPWPRQ1 65100Q (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 2 Submit Documentation Feedback Copyright © 2008–2012, Texas Instruments Incorporated Product Folder Link(s): TPS65100-Q1 |
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