UVLO1

Thermal

Shutdown

Shutdown

2.5 V

+

-

Current

Sense

Reference

V

ref

V

ref

ENA_1

ENA_1

10 k Ω

Rising Edge

Deglitch

0.95 × V

ref

FB2

Falling Edge

Delay

V

IN1

0.95 × V

ref

FB1

Rising Edge

Deglitch

Falling Edge

Deglitch

0.83 × V

ref

FB2

UV Comp

Falling Edge

Deglitch

0.83 × V

ref

FB1

UV Comp

Power

Sequence

Logic

ENA_1

ENA_2

V

IN1

Current

Sense

+

-

10 k Ω

ENA_2

ENA_2

FB2

V

ref

V

(2 Pins)

IN1

GND

EN

SEQ

(see Note B)

V

(2 Pins)

IN2

V

(2 Pins)

OUT1

V

SENSE1

(see Note A)

PG1

MR2

RESET

MR1

V

SENSE2

(see Note A)

V

(2 Pins)

OUT2

FB1

V

IN1

UVLO1

2.5 V

UVLO2

Shutdown

NOTES: A. For most applications, V

and V

should be externally connected to V

as close as possible to the device.

For other implementations, refer to SENSE terminal connection discussion in the Application Information section.

B. If the SEQ terminal is floating at the input, V

powers up first.

SENSE1

SENSE2

OUT

OUT2

TPS70358M

VOLTAGE (V)

PACKAGE-LEAD

ORDERABLE PART

TOP-SIDE

PRODUCT

(DESIGNATOR)

NUMBER

MARKING

TPS70358M

3.3 V

2.5 V

DFP-20 (HKH)

–55°C to 125°C

TPS70358MHKH

TPS70358MHKH

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

DETAILED BLOCK DIAGRAM - FIXED VOLTAGE VERSION

Copyright © 2009, Texas Instruments Incorporated

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