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TPS73418DRVT Datasheet(PDF) 2 Page - Texas Instruments |
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TPS73418DRVT Datasheet(HTML) 2 Page - Texas Instruments |
2 / 20 page ABSOLUTE MAXIMUM RATINGS (1) DISSIPATION RATINGS TPS734xx SBVS089F – DECEMBER 2007 – REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION(1) PRODUCT VOUT (2) TPS734xxyyyz XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable). YYY is package designator. Z is package quantity. (1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. (2) Output voltages from 1.0V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability. Over operating temperature range (unless otherwise noted). PARAMETER TPS734xx UNIT VIN range –0.3 to +7.0 V VEN range –0.3 to VIN +0.3 V VOUT range –0.3 to VIN +0.3 V VFB range –0.3 to VFB (TYP) +0.3 V Peak output current Internally limited Continuous total power dissipation See Dissipation Ratings Table Junction temperature range, TJ –55 to +150 °C Storage junction temperature range, TSTG –55 to +150 °C ESD rating, HBM 2 kV ESD rating, CDM 500 V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. DERATING FACTOR BOARD PACKAGE RθJC RθJA ABOVE TA = +25°C TA < +25°C TA = +70°C TA = +85°C Low-K(1) DDC 90°C/W 280°C/W 3.6mW/°C 360mW 200mW 145mW High-K(2) DDC 90°C/W 200°C/W 5.0mW/°C 500mW 275mW 200mW Low-K(1) DRV 20°C/W 140°C/W 7.1mW/°C 715mW 395mW 285mW High-K(2) DRV 20°C/W 65°C/W 15.4mW/°C 1.54W 845mW 615mW (1) The JEDEC low-K (1s) board used to derive this data was a 3in × 3in (7,62cm × 7,62cm), two-layer board with 2-ounce (56,699g) copper traces on top of the board. (2) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in (7,62cm × 7,62cm), multilayer board with 1-ounce (28,35g) internal power and ground planes and 2-ounce (56,699g) copper traces on top and bottom of the board 2 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated |
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