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TPS74901RGWT Datasheet(PDF) 6 Page - Texas Instruments |
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TPS74901RGWT Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 27 page  IN IN IN PG BIAS OUT OUT OUT NC FB 6 7 8 9 10 20 19 18 17 16 1 2 3 4 5 6 7 TPS749xx SBVS082G – JUNE 2007 – REVISED NOVEMBER 2010 www.ti.com PIN ASSIGNMENTS RGW PACKAGE KTW PACKAGE QFN-20 DDPAK-7 (TOP VIEW) (TOP VIEW) PIN DESCRIPTIONS NAME KTW (DDPAK) RGW (QFN) DESCRIPTION IN 5 5–8 Unregulated input to the device. Enable pin. Driving this pin high enables the regulator. Driving this pin low puts EN 7 11 the regulator into shutdown mode. This pin must not be left floating. SS 1 15 Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left floating, the regulator output soft-start ramp time is typically 100ms. BIAS 6 10 Bias input voltage for error amplifier, reference, and internal control circuits. Power-Good (PG) is an open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold the pin is driven to a PG N/A 9 low-impedance state. A pull-up resistor from 10k Ω to 1MΩ should be connected from this pin to a supply up to 5.5V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left floating if output monitoring is not necessary. This pin is the feedback connection to the center tap of an external resistor FB 2 16 divider network that sets the output voltage. This pin must not be left floating. OUT 3 1, 18–20 Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2mF, ceramic) is needed from this pin to ground to assure stability. No connection. This pin can be left floating or connected to GND to allow better NC N/A 2–4, 13, 14, 17 thermal contact to the top-side plane. GND 4 12 Ground PAD/TAB Should be soldered to the ground plane for increased thermal performance. 6 Submit Documentation Feedback Copyright © 2007–2010, Texas Instruments Incorporated |
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