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VSP2560PTR Datasheet(PDF) 8 Page - Texas Instruments |
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VSP2560PTR Datasheet(HTML) 8 Page - Texas Instruments |
8 / 32 page SERIAL INTERFACE TIMING t CKH t CKL t DS t DH t XH LSB A0 SDATA MSB D5 SCLK S LOAD t CKHX R LOAD t RL t WR t XS t CKP TwoBytes VSP2560 VSP2562 VSP2566 SBES008 – AUGUST 2008 ................................................................................................................................................................................................ www.ti.com Figure 2. Serial Interface Timing TIMING CHARACTERISTICS FOR Figure 2 PARAMETER(1)(2) MIN TYP MAX UNIT tCKP Clock period 50 ns tCKH Clock high pulse width 25 ns tCKL Clock low pulse width 25 ns tDS Data setup time 15 ns tDH Data hold time 15 ns tXS SLOAD to SCLK setup time 20 ns tXH SCLK to SLOAD hold time 20 ns tCKHX SCLK hold time of final SCLK 0 ns tRL SCLK to RLOAD setup time 20 ns tWR RLOAD pulse width 20 ns (1) tPD + tWD should be nearly equal to tDP + tWP. (2) The tWP and tWD specifications assume a driving impedance of less than 30 Ω at CCDIN. The data shift operation should decode at the rising edges of SCLK while SLOAD is low. Furthermore, the input address and data of the serial data stream are loaded to the parallel latch in the VSP2560/62/66 at the rising edge of SLOAD. 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2560 VSP2562 VSP2566 |
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