CLPOB

SHP

SHD

B11(MSB)

V

DD

DGND

ADCCK

V

CC

CLPDM

V

CC

REFP

REFN

B1

B0(LSB)

SCLK

SDATA

SLOAD

AGND

6

5

4

3

2

1

10

11

12

13

14

15

9

8

7

19

20

21

22

23

24

25

26

27

30

29

28

36

35

34

33

32

31

16

17

18

VSP2582

www.ti.com

SBES002B

– JUNE 2008 – REVISED JUNE 2011

PIN CONFIGURATION

RHH AND RHN PACKAGES

QFN-36

(TOP VIEW)

Table 1. TERMINAL FUNCTIONS

TERMINAL

NAME

NO.

DESCRIPTION

B2

1

DO

Data out bit 2

B3

2

DO

Data out bit 3

B4

3

DO

Data out bit 4

B5

4

DO

Data out bit 5

B6

5

DO

Data out bit 6

B7

6

DO

Data out bit 7

B8

7

DO

Data out bit 8

B9

8

DO

Data out bit 9

B10

9

DO

Data out bit 10

B11

10

DO

Data out bit 11 (MSB)

11

P

Digital power supply for data output

DGND

12

P

Digital ground for data output

ADCCK

13

DI

Clock for digital output buffer

14

P

Analog power supply

CLPDM

15

DI

CLPDM signal

CLPOB

16

DI

CLPOB signal

SHP

17

DI

Sampling clock for reference level of CCD signal

SHD

18

DI

Sampling clock for data level of CCD signal

AGND

19

P

Analog ground

20

P

Analog power supply

21

P

Analog power supply

AGND

22

P

Analog ground

(1)

Designators in TYPE: P: Power Supply and Ground, DI: Digital Input, DO: Digital Output, AI: Analog Input, AO: Analog Output.

Copyright

© 2008–2011, Texas Instruments Incorporated

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