SN74HC244Q1

OCTAL BUFFER AND LINE DRIVER

WITH 3STATE OUTPUTS

SCLS543A − SEPTEMBER 2002 − REVISED APRIL 2008

1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

LSTTL Loads

Memory Address Registers

description/ordering information

This octal buffer and line driver is designed

specifically to improve both the performance and

density of 3-state memory address drivers, clock

drivers, and bus-oriented receivers and transmitters.

The

SN74HC244

is

organized

as

two

4-bit

buffers/drivers with separate output-enable (OE)

inputs. When OE is low, the device passes

noninverted data from the A inputs to the Y outputs.

When

OE

is

high,

the

outputs

are

in

the

high-impedance state.

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40

°C to 125°C

SOIC − DW

Reel of 2000

SN74HC244QDWRQ1

HC244Q

−40

°C to 125°C

TSSOP − PW

Reel of 2000

SN74HC244QPWRQ1

HC244Q

† For the most current package and ordering information, see the Package Option Addendum at the end of this

document, or see the TI web site at http://www.ti.com.

‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.

FUNCTION TABLE

(each buffer/driver)

INPUTS

OUTPUT

OE

A

OUTPUT

Y

L

H

H

L

LL

H

X

Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

1OE

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

2OE

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

2A1

DW OR PW PACKAGE

(TOP VIEW)

Copyright

 2008, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.