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SN65HVD37_1207 Datasheet(PDF) 7 Page - Texas Instruments |
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SN65HVD37_1207 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 16 page Input Generator 50 Ω VO S1 3 V 3 V 3 V 50 % 50 % t PZL tPLZ 50 % 10 % 0 V VOL VI VO RL = 110 Ω ± 1% CL = 50 pF ±20% D Y Z DE VI C L Includes Fixture and Instrumentation Capacitance NOTE: D at 0 V to test non-inverting output, D at 3 V to test inverting output. 3 V Input Generator 50 Ω VO 1.5 V 0 V 50% 50% 3 V VOH VOL 50% 10% 50% tPLH tPHL tr tf 90% VI VO CL = 15 pF ±20% C Includes Fixture and Instrumentation Capacitance L A B RE VI R 0 V 90% 10% B A R VO 50 W VI Input Generator C L = 15 pF ±20% C L Includes Fixture and Instrumentation Capacitance RE S1 1 k W ±1% VCC V I tPZH(1) 3 V 50% 50% tPHZ 0V VO 50% ~0 V VOH 50% 0 V or 1.5 V 1.5 V or 0 V D at 3 V S1 to GND VO VCC V OL 1.5 V PLZ t PZL(1) t D at 0 V S1 to VCC SN65HVD37 www.ti.com SLLSE92 A – OCTOBER 2011 – REVISED NOVEMBER 2011 PARAMETER MEASUREMENT INFORMATION (continued) Figure 6. Measurement of Driver Enable and Disable Times with Active Low Output and Pull-up Load Figure 7. Measurement of Receiver Output Rise and Fall Times and Propagation Delays Figure 8. Measurement of Receiver Enable/Disable Times Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link(s): SN65HVD37 |
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