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SNHVD3082EDGKG4 Datasheet(PDF) 5 Page - Texas Instruments |
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SNHVD3082EDGKG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 26 page SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E www.ti.com SLLS562G – AUGUST 2009 – REVISED MAY 2009 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT Positive-going differential input threshold VIT+ IO = –8 mA –85 –10 mV voltage Negative-going differential input threshold VIT- IO = 8 mA –200 –115 mV voltage Vhys Hysteresis voltage (VIT+ - VIT-) 30 mV VOH High-level output voltage VID = 200 mV, IOH = –8 mA, See Figure 8 4 4.6 V VOL Low-level output voltage VID = –200 mV, IO = 8 mA, See Figure 8 0.15 0.4 V IOZ High-impedance-state output current VO = 0 or VCC, RE = VCC –1 1 μA VIH = 12 V, VCC = 5 V 0.04 0.1 VIH = 12 V, VCC = 0 V 0.06 0.125 II Bus input current mA VIH = –7 V, VCC = 5 V –0.1 –0.04 VIH = –7 V, VCC = 0 V –0.05 –0.03 IIH High-level input current, (RE) VIH = 2 V –60 –30 μA IIL Low-level Input current, (RE) VIL = 0.8 V –60 –30 μA Cdiff Differential input capacitance VI = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 7 pF (1) All typical values are at 25°C and with a 5-V supply. RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT HVD3082E 75 200 Propagation delay time, low-to-high- HVD3085E tPLH ns level output HVD3086E 100 HVD3082E 79 200 Propagation delay time, high-to-low- CL = 15 pF, See HVD3085E tPHL ns level output Figure 9 HVD3088E 100 HVD3082E 4 30 HVD3085E tsk(p) Pulse skew (|tPHL – tPLH|) ns HVD3088E 10 tr Output signal rise time 1.5 3 ns VID = –1.5 V to 1.5 V, CL = 15 pF, See Figure 9 tf Output signal fall time 1.8 3 ns HVD3082E 5 50 HVD3085E tPZH Output enable time to high level ns HVD3088E 30 HVD3082E 10 50 HVD3085E tPZL Output enable time to low level ns CL = 15 pF, HVD3088E 30 DE at 3 V See Figure 10 and HVD3082E 5 50 Figure 11 HVD3085E tPHZ Output enable time from high level ns HVD3088E 30 HVD3082E 8 50 HVD3085E tPLZ Output disable time from low level ns HVD3088E 30 Propagation delay time, shutdown-to- tPZH(SHDN) 1600 3500 ns high-level output CL = 15 pF, DE at 0 V, See Figure 12 Propagation delay time, shutdown-to-low- tPZL(SHDN) 1700 3500 ns level output Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E |
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