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TM16LR64JFN Datasheet(PDF) 2 Page - Texas Instruments |
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TM16LR64JFN Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 17 page  TM8LR64JFN 8 388 608 BY 64BIT TM16LR64JFN 16 777 216 BY 64BIT SYNCHRONOUS DYNAMIC RAM MODULES SMMS710 − MAY 1998 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 DUAL-IN-LINE MEMORY MODULE ( TOP VIEW ) TM16LR64JFN ( SIDE VIEW ) 1 10 11 40 84 41 PIN NOMENCLATURE A[0:11] Row-Address Inputs A[0:8] Column-Address Inputs A13/BA0 Bank-Select Zero A12/BA1 Bank-Select One CAS Column-Address Strobe CB[0:7] Check Bit In/Check Bit Out CKE[0:1] Clock Enable CK[0:3] System Clock DQ[0:63] Data-In / Data-Out DQMB[0:7] Data-In/Data-Out Mask Enable NC No Connect RAS Row-Address Strobe S[0:3] Chip-Select SA[0:2] Serial Presence Detect (SPD) Device Address Input SCL SPD Clock SDA SPD Address / Data VDD 3.3-V Supply VSS Ground WE Write Enable WP Write Protect TM8LR64JFN ( SIDE VIEW ) |
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