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TNETA1500APGE Datasheet(PDF) 4 Page - Texas Instruments

Part # TNETA1500APGE
Description  155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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TNETA1500APGE Datasheet(HTML) 4 Page - Texas Instruments

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TNETA1500A
155.52-MBIT/S SONET/SDH ATM RECEIVER/TRANSMITTER
SDNS042A – AUGUST 1997 – REVISED JANUARY 1998
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description
transmit operation
The transmit-cell interface consists of the byte-wide input data (TD0–TD7), input clock (TCKI), start of ATM-cell
input (TXCELL), transmit write-enable input (TWE), and transmit-input FIFO almost-full output (TXAF). Input
data is clocked into the TNETA1500A on low-to-high transitions of TCKI when TWE is low. The transmit-input
FIFO almost-full flag (TXAF) goes active when the transmit FIFO is within five bytes of filling up (the FIFO holds
three complete ATM cells).
The 48-byte information field of the ATM cell is scrambled using a self-synchronizing scrambler polynomial of
x43 + 1 to improve the efficiency of the cell-delineation procedure. At startup, the scrambler is initialized to an
all-1s state. The 5-byte ATM header is not scrambled at this step. TXCELL identifies the first byte of the ATM
cell and disables the scrambler. The input data is stored in the transmit-input FIFO and multiplexed into the
SONET/SDH payload after all 53 bytes have been received. If the FIFO does not contain 53 bytes of information
at the start of a cell-insertion cycle, an idle or unassigned cell is sent, dependent on the status of the control
registers. An idle cell is defined as an ATM cell with the 5-byte header set to 00 00 00 01 52 (hex) and the 48-byte
payload set to 6A (hex). An unassigned cell is defined as an ATM cell with the 5-byte header set to
00 00 00 00 55 (hex) and the 48-byte payload set to 6A (hex). See
controller-interface operation for more
information on the operation of the control registers.
The transmit section calculates the header-error-check (HEC) byte in the ATM header by default. This implies
that the fifth byte of the ATM cell that is input through the transmit-cell interface is ignored. The HEC byte is
calculated in accordance with the ANSI T1.624-1993 and CCITT recommendation I.432. This feature can be
disabled by setting a bit in the control register.
The transmit operation can be programmed to send either a SONET STS-3c frame or an SDH STM-1 frame.
When SDHENABLE is low, a SONET STS-3c frame is transmitted. When SDHENABLE is high, an STM-1 frame
is transmitted. For both the STS-3c and STM-1 frames, the location of the J1 byte in the path overhead is fixed;
the J1 byte always comes after the third C1 byte of the transport overhead (TOH). This is known as location 522.
The data-communication channels (D1 through D12 bytes) in the TOH are set to a hex value of FF 00 00. The
values for the transport- and path-overhead bytes for both an STS-3c frame and an STM-1 frame are given in
Table 1.
The parity bytes B1, B2 (three bytes), and B3 are calculated as follows:
B1 — B1 is a bit-interleaved parity-8 (BIP-8) code using even parity. B1 is calculated over all bits of the
previous STS-3c frame after scrambling. The calculated value of B1 is placed in the STS-3c frame before
the frame is scrambled.
B2 — For an STS-3c frame, the three B2 bytes combine to form a BIP-24 code; however, each B2 byte is
calculated as if the frame is composed of three individual STS-1s. Each B2 is calculated over all bits of the
line overhead and STS-1 envelope capacity of the previous STS-1 frame before scrambling, using even
parity. The computed value is placed in the appropriate B2 byte location before scrambling. The line
overhead consists of the six rows of TOH bytes, beginning with the first H1 byte and ending before the row
containing the first A1 byte (see Table 1).
B3 — For an STS-3c frame, the B3 byte is calculated over all bits of the previous STS-3c SPE before
scrambling. B3 is a BIP-8 code, using even parity. The computed value is placed in the B3 location
before scrambling.


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