Electronic Components Datasheet Search |
|
TNETA1585 Datasheet(PDF) 8 Page - Texas Instruments |
|
TNETA1585 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 32 page TNETA1585 ATM TRAFFIC MANAGEMENT SCHEDULER DEVICE WITH RECEIVE UTOPIA AND COPROCESSOR INTERFACES SDNS041A – NOVEMBER 1996 – REVISED JULY 1998 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 slave-control interface (continued) Table 1. Slave-Control Interface Register Map DESCRIPTION HOST/SAR ASSOCIATED R/W CONTROL MEMORY ADDRESS (TNETA1575) PCI OFFSET ADDRESS (TNETA1575) Next-cell register SAR R h10000 h40000 RM-cell-contents FIFO A SAR R h10001 h40004 RM-cell-contents FIFO B SAR R h10002 h40008 RM-cell-contents FIFO C SAR R h10003 h4000C RM-cell-contents FIFO D SAR R h10004 h40010 Reserved N/A N/A h10005–7 h40014–1C Configuration register Host R/W h10008 h40020 Status register Host R h10009 h40024 Interrupt-mask register Host R/W h1000A h40028 Schedule-on register Host W h1000B h4002C Schedule-off register Host W h1000C h40030 Read-address register Host R/W h1000D h40034 Read-data register Host R h1000E h40038 Write-address register Host R/W h1000F h4003C Write-data register Host W h10010 h40040 Clock-frequency register Host R/W h10011 h40044 Revision-number register Host R h10012 h40048 ACR-low register Host R h10013 h4004C ACR-OK register Host R h10014 h40050 Reserved N/A N/A h10015–19 h40054–64 General-purpose registers Host R/W h1001A–1D h40068–74 Reserved N/A N/A h100IE–3F h40078–FC The following describes the SAR-associated registers with respect to what the TNETA1575 requires of the interface. However, these registers can be used by other COPI-compliant ATM-layer devices to assist in the scheduling of cells and the generation of RM cells. next-cell register The TNETA1575 uses the next-cell register to determine if one of the TNETA1585’s scheduled connections is ready to transmit and, if so, which channel and what type of cell (i.e., data, forward RM, backward RM). This register is read only. READY CELL COUNT RESERVED CHANNEL NUMBER CLP CELL TYPE BIT 31 30–26 25–15 14–4 3 2–0 Bit 31 (ready). The TNETA1585 sets bit 31 to indicate that the contents of the register are valid and ready to read. Bits 30–26 (cell count). This field indicates the number of cells (minus one) that are to be sent by the SAR for this particular channel. A zero entry tells the SAR to send a single cell and an all-ones entry tells the SAR to send 32 cells. |
Similar Part No. - TNETA1585 |
|
Similar Description - TNETA1585 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |