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313953-001 Datasheet(PDF) 10 Page - Intel Corporation |
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313953-001 Datasheet(HTML) 10 Page - Intel Corporation |
10 / 16 page Order Number: 313954-004 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) 10 Specifiication Update 5. LOCK to non-DRAM Memory Flag (Register C8, Bit 9) is Getting Asserted Problem: A CPU lock cycle request is unintentionally being recognized as request to a non- system memory destination. Implication: The MCH may incorrectly flag an error for a valid lock cycle that targets DRAM. A System Error (SERR) may be generated if enabled by System BIOS. Note: The default setting for ERRCMD[9] Bus 0 Device 0 Offset CAh is to disable this reporting. Workaround: Do not enable or change default setting of ERRCMD[9] Bus 0 Device 0 Offset CAh (SERR reporting for Lock cycles to non-DRAM Memory) Status: NoFix. For affected steppings, see the Summary Table of Changes. 6. The PCI Express* Port Does Not Send The Correct TLP Type Downstream When There is a Memory Read Request-Locked TLP Problem: Upstream Transaction Layer Packet (TLP) Type, Memory Read Request-Locked (MRdLk), is a unsupported request for the MCH on the PCI Express* Port. The Transaction Layer receives the MRdLk and sends downstream a Completion without Data (Cpl) TLP type with an unsupported request status. The correct behavior should be to send a Completion for Locked Memory Read without Data (CplLk) TLP type with an unsupported request status. Implication: None. PCI Express* 1.0a compliant devices are not allowed to send locked requests upstream. Workaround: None. Status: NoFix. For affected steppings, see the Summary Table of Changes. 7. PCI Express* Port Skip Sequence is Not Transmitted When Entering Recovery State Problem: PCI Express* Port Skip Sequence in a non-common clock configuration is not transmitted when the skip latency counter expires exactly at the same time the MCH is entering the recovery state. The MCH sends the COM symbol (K28.5) followed by idles instead of skip sequence symbol (K28.0). Note: This has only been reproduced in a synthetic test environment and only applies to systems that use a non-common clock configuration. Implication: None. Skip Sequence Symbol generation is not a requirement for proper operation in systems that implement common clock configurations. Workaround: None. Status: NoFix. For affected steppings, see the Summary Table of Changes 8. STPCLK# Throttling May Cause System to Hang Problem: In platforms that use STPCLK# throttling in conjunction with devices that invoke the PHOLD mechanism in the ICH (e.g., floppy drives), a boundary condition can occur in the system resulting in the number of STPCLK# acknowledges to be out of synchronization. The failure occurs if a STPCLK# acknowledge cycle is retried on the front side bus at the same time as an internal MCH throttling counter is incremented. Note: This has only been reproduced in a synthetic test environment under extreme thermal throttling conditions. Implication: The system may hang. Workaround: STPCLK# throttling is not necessary in desktop systems that meet Intel's thermal guidelines and therefore should be disabled by the BIOS. Contact your Intel Field Representative for the latest BIOS information. |
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