VSP7500

VSP7502

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SBES015A – DECEMBER 2010 – REVISED JANUARY 2011

OPTICAL BLACK (OB) LOOP AND OB CLAMP (OBCLP) LEVEL

The VSP7500/VSP7502 have a built-in optical black (OB) offset self-calibration circuit (OB loop) that

compensates the OB level by using OB pixels that are output from the CCD image sensor. This device also

provides a digital OB clamp loop. CCD offset is compensated by converging both OB loops while activating

CLPOB during a period when OB pixels are output from the CCD. 20 pixels of the CLPOB period may be enough

for stable OB loop operation.

CLOCKING AND DLL

The VSP7500/VSP7502 require the following clocks for proper operation: MCLK, the system clock; CLPOB, the

optical black level clamp; and CLPDM, the input clamp.

The HBLK timing signal transmits the horizontal blanking period timing. In this period, high-speed HTG pulses

are masked. The PBLK timing signal transmits the data output blanking period timing. In this period, outputting

the ADC data is masked.

The VSP7500/VSP7502 have built-in DLL circuits that enable the required sampling clocks and the horizontal

timing pulse and logic clocks for outputting LVDS data to be generated.

VOLTAGE REFERENCE

All reference voltages and bias currents used on the VSP7500/VSP7502 are created from internal bandgap

circuitry. The device has a symmetrically independent voltage reference for each channel.

Both channels of the S/H, CDS, and the ADC use three primary reference voltages: REFP (1.25 V), REFN

(0.75 V), and CM (1 V) of individual references. REFP and REFN are buffered on-chip. CM is derived as the

midrange voltage of the resistor chain internally connecting REFP and REFN. The ADC full-scale range is

determined by twice the difference voltage between REFP and REFN.

REFP, REFN, and CM should be heavily decoupled with appropriate capacitors.

HOT PIXEL REJECTION

Sometimes, OB pixel output signals from the CCD include unusual level signals that are caused by pixel

defection. If this level reaches a full-scale level, it may affect OB level stability. The VSP7500/VSP7502 have a

function that rejects the unusually large pixel levels (hot pixels) in the OB pixel. This function may contribute to

CCD yield improvement that is caused by OB pixel failure.

Rejection level for hot pixels is programmable through the serial interface. When hot pixels come from the CCD,

the VSP7500/VSP7502 omit them and replace the previous pixel level with the OB level calculation.

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Product Folder Link(s): VSP7500 VSP7502