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NS32FV100 Datasheet(PDF) 10 Page - Texas Instruments |
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NS32FV100 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 96 page  10 Fax-System Configuration (Continued) power-fail input is asynchronous It is recognized by the NS32FX100 during cycles in which the input setup-time re- quirement is satisfied Switching from Normal mode to Power Save mode and vice versa must always be carried out using the NS32FX100 explicitly The clock scaling option of the CPU should not be used for this purpose 131 Functionality State S1 Normal Mode The system operates at the full clock frequency The NS32FX100 is powered by the main power supply Software can switch the system to state S7 Power Save Mode The NS32FX100 switches to state S2 Power Fail when PFAIL is asserted State S2 Power Fail In this state the CPU enters an NMI handler in which the software performs all the bookkeeping required for recovery and switches to full clock frequency The software should write H’80 to MCFG Once finished the software activates the WATCHDOG trap output signal which asserts the RST input of the CPU by writing three times to the WATCHDOG When both PFAIL and RST are active the NS32FX100 and the RAM must be powered from a battery The CPU can be powered down When RST is detected the system chip goes from S2 to one of the following states State S3 if DRAM refresh is enabled (only in NS32FV100 and NS32FX200) State S5 if no DRAM refresh is needed (NS32FX100al- ways) State S3 Complete Refresh Transaction If RST is de- tected while refresh is enabled in state S2 a refresh trans- action is performed The system chip then switches to state S4 State S4 Freeze and Refresh In this state the system chip de-activates the fast crystal oscillator and freezes the CCLK clock Only the Elapsed Time Counter and the DRAM refresh generator are functional When the ETC count reaches zero the state machine switches to state S5 and refresh transactions are stopped Thus the contents of the DRAM can be kept for a prede- fined period (software programmable) If the power failure lasts longer than this period the system should disconnect the DRAM and leave only the ETC and possibly an SRAM device connected to the battery If PFAIL goes high the state machine switches to state S6 Power Restore State S5 FreezeNo Refresh In this state only the ETC counter is activecounting the duration of the power fail- ure In this state the NS32FX100 functions with a supply voltage as low as 3V If PFAIL goes high the state machine switches to state S6 Power Restore State S6 Power Restore This state can be entered either from Freeze Mode or during normal operation when reset is asserted When entering from Freeze Mode (PFAIL goes high) RST is kept low for a few milliseconds by an external circuit During this time the fast crystal oscillator is activated and the CPU and NS32FX100 clocks are synchronized If refresh is enabled the system chip will initiate refresh transactions during this timethe refresh rate is forced to a default value When RST goes high the NS32FX100 switches to state S7 Power Save Mode State S7 Power Save Mode The CPU runs at a slow fre- quency116 of the Normal Mode frequency The system can swtich to S1 Normal Mode under software control If PFAIL input is asserted the NS32FX100 switches to state S2 Power Fail TLEE11331 – 5 FIGURE 1-5 System Chip States and Operation Modes 9 |
Similar Part No. - NS32FV100 |
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Similar Description - NS32FV100 |
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