NSBMC096 datasheet(11/20 Pages) TI1

Part #	NSBMC096

Description	NSBMC096 Burst Memory Controller

Download	20 Pages

Scroll/Zoom	100%

Manufacturer	TI1 [Texas Instruments]

Direct Link	http://www.ti.com

Logo

11 / 20 page

Application Example

System Clock

25 MHz

Refresh Rate

16 ms per row (0 c 18)

Memory Size

1 MB x 1 (Size e 1)

Buffer Mode

Signal 1 e CEA Signal 2 e CEB

(Mode 1)

Interleave

Enabled

Row Address Hold

clock cycle

(Row Address Hold e 0)

Cycle Extend

Disabled

(3 clock RAS derived from

tRSHL of NSBMC096 RAS access time

of DRAM buffer delay of 74FCT245

and setup time of the processor’s data

inputs)

Burst Write

Disabled

Base Address

8 MB (0b000000000100)

Required Configuration for startup

0000

1000

1001

0110

0000

(0x00889600)

Configuration Setup

0xFF0F0000 (0xFF0F0000 0)

Config bits 70 e 0

0xFF0F0658 (0xFF0F0400 a (0x96m2) 0)

Config bits 158 e 0

0xFF0F0A20 (0xFF0F0800 a (0x88m2) 0)

Config bits 2316 e 0

0xFF0F0C00 (0xFF0F0C00 0)

Config bits 3124 e 0

The ease with which the NSBMC096 may be integrated into

a system design is illustrated in the diagram in

Figure 4 The

system shown supports an i960 CACF with between 2 and

128 MB of memory depending on the devices selected

managed by a single NSBMC096 This specific example ac-

commodates 1 MB x 1 4 MBx1or16MBx1 devices

Connection of the NSBMC096 to the i960 CACF processor

is accomplished simply by wiring together pins with the

same names The only exceptions are READY and BTERM

If the NSBMC096 is the only device that generates these

two signals they can be connected directly to the appropri-

ate inputs of the processor and require only a small pull up

resistor to keep them de-asserted when in the high imped-

ance state

If multiple processor peripherals are connected to READY

or BTERM 3-state drivers should be used in such a manner

that the signals are actively de-asserted prior to the driver

being placed in its’ high impedance state If this rule is fol-

lowed a simple ‘‘wire or’’ can be used Alternately all

sources of READY or BTERM can be combined using multi-

ple input gates and the processor signals driven by the out-

puts

TLV11805 – 7

FIGURE 4 Possible System Interconnection using V96BMC

(Mode 1 where TXA is used as CEA and TXB as CEB)

10

Similar Part No. - NSBMC096

Manufacturer	Part #	Datasheet	Description
National Semiconductor ...	NSBMC096-16	266Kb / 18P	NSBMC096-16/-25/-33 Burst Memory Controller
National Semiconductor ...	NSBMC096VF	266Kb / 18P	NSBMC096-16/-25/-33 Burst Memory Controller

More results

Similar Description - NSBMC096

Manufacturer	Part #	Datasheet	Description
National Semiconductor ...	NSBMC096-16	266Kb / 18P	NSBMC096-16/-25/-33 Burst Memory Controller
National Semiconductor ...	NSBMC290-16	318Kb / 20P	Burst Mode Memory Controller
NXP Semiconductors	SAA4951	95Kb / 25P	Memory controller April 1994
	SAA4952WP	159Kb / 32P	Memory controller 1997 Jun 10
	PCD5042	134Kb / 28P	DECT burst mode controller 1996 Oct 31
	PCD5041	134Kb / 28P	DECT burst mode controller 1996 Oct 31
	PCD5043	109Kb / 24P	DECT burst mode controller 1996 Oct 31
OptoSupply Internationa...	OSUBECX	45Kb / 2P	Memory RGB controller
Sanyo Semicon Device	LC82293	197Kb / 2P	Image Memory Controller
Advanced Micro Devices	AM2964B	760Kb / 14P	Dynamic Memory Controller Rev. C

More results

NSBMC096 Datasheet(PDF) 11 Page - Texas Instruments

NSBMC096 Datasheet(HTML) 11 Page - Texas Instruments

Similar Part No. - NSBMC096

Similar Description - NSBMC096

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL