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NS32FX161-20 Datasheet(PDF) 10 Page - Texas Instruments |
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NS32FX161-20 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 104 page  20 Architectural Description (Continued) B Reserved for use by the CPU This bit is set to 1 during the execution of the EXTBLT instruction and causes the BPU signal to become active Upon reset B is set to zero and the BPU signal is set high Note 1 When an interrupt is acknowledged the B I P S and U bits are set to zero and the BPU signal is set high A return from interrupt will restore the original values from the copy of the PSR register saved in the interrupt stack Note 2 If BITBLT (BB) or EXTBLT instructions are executed in an interrupt routine the PSR bits J and K must be cleared first 214 Configuration Register The Configuration Register (CFG) is 32 bits wide of which 5 bits are implemented The implemented bits enable various operating modes for the CPU including vectoring of inter- rupts execution of floating-point instructions processing of exceptions and selection of clock scaling factor The CFG is programmed by the SETCFG instruction The format of CFG is shown in Figure 2-3 The various control bits are de- scribed below 31 8 7 0 Reserved DE Res C M F I FIGURE 2-3 Configuration Register (CFG) I Interrupt vectoring This bit controls whether maskable interrupts are handled in nonvectored (Ie0) or vec- tored (Ie1) mode Refer to Section 323 for more in- formation F Floating-point instruction set This bit indicates wheth- er a floating-point unit (FPU) is present to execute floating-point instructions If this bit is 0 when the CPU executes a floating-point instruction a Trap (UND) oc- curs If this bit is 1 then the CPU transfers the instruc- tion and any necessary operands to the FPU using the slave-processor protocol described in Section 3131 M Clock scaling This bit is used in conjunction with the C-bit to select the clock scaling factor C Clock scaling Same as the M-bit above Refer to Sec- tion 353 on ‘‘Power Save Mode’’ for details DE Direct-Exception mode enable This bit enables the Di- rect-Exception mode for processing exceptions When this mode is selected the CPU response time to inter- rupts and other exceptions is significantly improved Refer to Section 32 for more information 215 DSP Module Registers The DSP Module (DSPM) contains 15 memory-mapped reg- isters All the registers except OVF CLSTAT ABORT DSPINT and NMISTAT are readable and writable OVF CLSTAT DSPINT and NMISTAT are read-only ABORT is write-only The DSPM registers are divided into two groups according to their function PARAM OVF X Y Z A REPEAT CLPTR and EABR are called DSPM dedicated registers CLSTAT ABORT DSPINT DSPMASK EXT and NMISTAT are called CPU core interface registers Accesses to these registers must be aligned word and dou- ble-word accesses must occur on word and double-word address boundaries respectively Failing to do so will cause unpredictable results Figure 2-4 shows the address map of the DSP Module registers Register Register Name Address PARAM FFFF8000 OVF FFFF8004 X FFFF8008 Y FFFF800C Z FFFF8010 A FFFF8014 REPEAT FFFF8018 CLPTR FFFF8020 EABR FFFF8024 CLSTAT FFFF9000 ABORT FFFF9004 DSPINT FFFF9008 DSPMASK FFFF900C EXT FFFF9010 NMISTAT FFFF9014 FIGURE 2-4 DSP Module Registers Address Map AAccumulator The format of the accumulator is shown in Figure 2-5 33 0 33 0 Imaginary Real FIGURE 2-5 Accumulator Format The A register is a complex accumulator It has two 34-bit fields a real part and an imaginary part Bits 15 through 30 of the real and the imaginary parts of the accumulator can be read or written by the core in one double-word access Bits 15 through 30 of the real part are mapped to the oper- and’s bits 0 through 15 and bits 15 through 30 of the imagi- nary part are mapped to the operand’s bits 16 through 31 The accumulator can also be read and written by the com- mand-list execution unit using the SA SEA LA and LEA instructions (See Section 34 for more information) Note that when a value is stored in the accumulator by the core the value of PARAMRND bit is copied into bit position 14 of both real and imaginary parts of the accumulator This technique allows rounding of the accumulator’s value in the following DSPM instructions (See Section 3453 for more information on rounding) When the Accumulator is loaded either by the core or by the LA or LEA instructions bits 31 – 33 of the real and the imagi- nary accumulators are loaded with the values of bit 30 of the real and the imaginary parts respectively When the Accumulator is loaded either by the core or by the LA instruction bits 0 – 13 of the real and the imaginary accu- mulators are loaded with zeros X Y ZVector Pointers The format of X Y and Z registers is shown in Figure 2-6 31 16 15 8 7 4 3 0 ADDRESS Reserved WRAP-AROUND INCREMENT FIGURE 2-6 X Y Z Registers Format 9 |
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