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SN74BCT899DWR Datasheet(PDF) 2 Page - Texas Instruments |
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SN74BCT899DWR Datasheet(HTML) 2 Page - Texas Instruments |
2 / 8 page SN74BCT899 9BIT LATCHABLE TRANSCEIVER WITH PARITY GENERATOR/CHECKER SCBS253 − JUNE 1992 − REVISED NOVEMBER 1993 2−2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 FUNCTION TABLE INPUTS OPERATION OR FUNCTION OEAB OEBA SEL LEAB LEBA OPERATION OR FUNCTION H H X X X Buses A and B are in the high-impedance state. H L L X H Generates parity from B1 − B8 based on ODD/EVEN. Generated parity → APAR. Generated parity checked against BPAR and output as ERRB. H L L H H Generates parity from B1 − B8 based on ODD/EVEN. Generated parity → APAR. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. H L L X L Generates parity from B-latch data based on ODD/EVEN. Generated parity → APAR. Generated parity checked against latched BPAR and output as ERRB. H L H X H BPAR /B1 − B8 → APAR/A1−A8 feed-through mode. Generated parity checked against BPAR and output as ERRB. H L H H H BPAR /B1 − B8 → APAR/A1−A8 feed-through mode. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. L H L H X Generates parity from A1 − A8 based on ODD/EVEN. Generated parity → BPAR. Generated parity checked against APAR and output as ERRA. L H L H H Generates parity from A1 − A8 based on ODD/EVEN. Generated parity → BPAR. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. L H L L X Generates parity from A-latch data based on ODD/EVEN. Generated parity → BPAR. Generated parity checked against latched APAR and output as ERRA. L H H H X APAR /A1 − A8 → BPAR/B1−B8 feed-through mode. Generated parity checked against APAR and output as ERRA. L H H H X APAR /A1 − A8 → BPAR/B1−B8 feed-through mode. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. L L X X X Output to A bus and B bus PARITY FUNCTION TABLE INPUTS† OUTPUTS ODD/EVEN Σ OF INPUTS A1 − A8 = H APAR BPAR‡ ERRA L 0, 2, 4, 6, 8 L L H L 1, 3, 5, 7 L H L L 0, 2, 4, 6, 8 H L L L 1, 3, 5, 7 H H H H 0, 2, 4, 6, 8 L H L H 1, 3, 5, 7 L L H H 0, 2, 4, 6, 8 H H H H 1, 3, 5, 7 H L L † If LE = H, current A1 −A8 and APAR data is used. If LE = L, latched A1−A8 and APAR data is used. ‡ This is the value of BPAR if SEL = L. If SEL = H, BPAR = APAR. |
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