TM124FBK32F, TM124FBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE

TM248GBK32F, TM248GBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE

SMMS660 – MARCH 1996

1

POST OFFICE BOX 1443

TM124FBK32F ...1048 576

× 32

TM248GBK32F ...2097 152

× 32

(SIMM) for Use With Socket

Dynamic Random-Access Memories

(DRAMs) in Plastic Small-Outline J-Lead

(SOJ) Package

DRAMs in Plastic SOJ Package

16 ms (1 024 Cycles)

TTL-Compatible

Data-In and Data-Out Lines in Four Blocks

CAS-Before-RAS ( CBR ), RAS-Only, Hidden

Refresh, and Self Refresh

Pinout

ACCESS

ACCESS ACCESS

EDO

TIME

TIME

TIME

CYCLE

tRAC

tAA

tCAC

tHPC

(MAX)

(MAX)

(MAX)

(MIN)

’124FBK32F-60

60 ns

30 ns

15 ns

25 ns

’124FBK32F-70

70 ns

35 ns

18 ns

30 ns

’124FBK32F-80

80 ns

40 ns

20 ns

35 ns

’248GBK32F-60

60 ns

30 ns

15 ns

25 ns

’248GBK32F-70

70 ns

35 ns

18 ns

30 ns

’248GBK32F-80

80 ns

40 ns

20 ns

35 ns

0

°C to 70°C

TM124FBK32F

TM248GBK32F

TM124FBK32U

TM248GBK32U

description

TM124FBK32F

The TM124FBK32F is a 4M-byte DRAM organized as four times 1 048 576

× 8 in a 72-pin SIMM. The SIMM is

composed of two TMS418169DZ 1 048 576

× 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted

on a substrate with decoupling capacitors. The TMS418169DZ is described in the TMS418169 data sheet

(literature number SMKS886). The TM124FBK32F SIMM is available in the single-sided BK-leadless module

for use with sockets.

TM248GBK32F

The TM248GBK32F is an 8M-byte DRAM organized as four times 2 097 152

× 8 in a 72-pin SIMM. The SIMM

is composed of four TMS418169DZ 1 048 576

× 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted

on a substrate with decoupling capacitors. The TMS418169DZ is described in the TMS418169 data sheet

(literature number SMKS886). The TM248GBK32F SIMM is available in the double-sided BK-leadless module

for use with sockets.

operation

The TM124FBK32F operates as two TMS418169DZs connected as shown in the functional block diagram and

in Table 1. The TM248GBK32F operates as four TMS418169DZs connected as shown in the functional block

diagram and in Table 1. The common I / O feature dictates the use of early-write cycles to prevent contention

on D and Q.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

† Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Copyright

© 1996, Texas Instruments Incorporated