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TM124MBK36U-70 Datasheet(PDF) 7 Page - Texas Instruments |
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TM124MBK36U-70 Datasheet(HTML) 7 Page - Texas Instruments |
7 / 9 page TM124MBK36F, TM124MBK36U 1048576 BY 36-BIT DRAM MODULE TM248NBK36F, TM248NBK36U 2097152 BY 36-BIT DRAM MODULE SMMS650A – APRIL 1995 – REVISED JUNE 1995 7 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 switching characteristics over recommended ranges of supply voltage and operating free-air temperature PARAMETER ’124MBK36F - 60 ’248NBK36F - 60 ’124MBK36F - 70 ’248NBK36F - 70 ’124MBK36F - 80 ’248NBK36F - 80 UNIT MIN MAX MIN MAX MIN MAX tAA Access time from column address 30 35 40 ns tCAC Access time from CAS low 15 18 20 ns tRAC Access time from RAS low 60 70 80 ns tCPA Access time from column precharge 35 40 45 ns tCLZ CAS to output in low-impedance state 0 0 0 ns tOH Output disable time from start of CAS high 3 3 3 ns tOFF Output disable time after CAS high (see Note 6) 0 15 0 18 0 20 ns NOTE 6: tOFF is specified when the output is no longer driven. timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124MBK36F - 60 ’248NBK36F - 60 ’124MBK36F - 70 ’248NBK36F - 70 ’124MBK36F - 80 ’248NBK36F - 80 UNIT MIN MAX MIN MAX MIN MAX tRC Cycle time, random read or write (see Note 7) 110 130 150 ns tPC Cycle time, page-mode read or write (see Notes 7 and 8) 40 45 50 ns tRASP Pulse duration, page mode, RAS low 60 100 000 70 100 000 80 100 000 ns tRAS Pulse duration, nonpage mode, RAS low 60 10 000 70 10 000 80 10 000 ns tCAS Pulse duration, CAS low 15 10 000 18 10 000 20 10 000 ns tCP Pulse duration, CAS high (precharge) 10 10 10 ns tRP Pulse duration, RAS high (precharge) 40 50 60 ns tWP Pulse duration, W low 10 10 10 ns tASC Setup time, column address before CAS low 0 0 0 ns tASR Setup time, row address before RAS low 0 0 0 ns tDS Setup time, data before CAS low 0 0 0 ns tRCS Setup time, W high before CAS low 0 0 0 ns tCWL Setup time, W low before CAS high 15 18 20 ns tRWL Setup time, W low before RAS high 15 18 20 ns tWCS Setup time, W low before CAS low 0 0 0 ns tWRP Setup time, W high before RAS low (CBR refresh only) 10 10 10 ns tCAH Hold time, column address after CAS low 10 15 15 ns tRHCP Hold time, RAS high from CAS precharge 35 40 45 ns tDH Hold time, data after CAS low 10 15 15 ns tRAH Hold time, row address after RAS low 10 10 10 ns tRCH Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH Hold time, W high after RAS high (see Note 9) 0 0 0 ns tWCH Hold time, W low after CAS low 10 15 15 ns tWRH Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be ≥ tCP. 9. Either tRRH or tRCH must be satisfied for a read cycle. |
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