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SN65HVD09IDGGREP Datasheet(PDF) 10 Page - Texas Instruments |
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SN65HVD09IDGGREP Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 26 page  1.5V 1.5V 0V 0V 0V 0V tPZH tPHZ tPZL tPLZ 3V 0V VOD(H) ∼ − 1V ∼ 1V VOD(L) Input,DE/RE Output,VOD Output,VOD A at 3V S1 to PD A at 0V S1 to PU † A 620 Ω VT Output 40pF‡ B + B − DE/RE 0Vor3V 3Vor0V Input † ‡ CDEOishigh,CDE1,CDE2,BSR,and arelow, allothersareopen. CRE Includesprobeandjigcapacitance. SN65HVD09-EP SLLSEA3 – DECEMBER 2011 www.ti.com Table 1. Enabling for Driver Enable and Disable Time DRIVER BSR CDE0 CDE1 CDE2 CRE 1 –8 H H L L X 9 L H H H H Figure 7. Driver Enable Time Waveforms NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr ≤ 6 ns, tf ≤ 6 ns, PRR ≤ 1 MHz, duty cycle = 50%, ZO = 50 Ω. B. All resistances are in Ω and ±5%, unless otherwise indicated. C. All capacitances are in pF and ±10%, unless otherwise indicated. D. All indicated voltages are ±10 mV. Figure 8. Receiver Enable and Disable Time Test Circuit 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s) :SN65HVD09-EP |
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