Switching Characteristics

1

7

tc * 0.2

1

7

tc ) 0.2

2

7

tc * 0.2

2

7

tc ) 0.2

3

7

tc * 0.2

3

7

tc ) 0.2

4

7

tc * 0.2

4

7

tc ) 0.2

5

7

tc * 0.2

5

7

tc ) 0.2

6

7

tc * 0.2

6

7

tc ) 0.2

Output skew, tn *

n

7

tc

4

7

tc

SN65LVDS84AQ-Q1

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Delay time, CLKOUT

↑ to

–0.2

0.2

serial bit position 0

Delay time, CLKOUT

↑ to

serial bit position 1

Delay time, CLKOUT

↑ to

serial bit position 2

Delay time, CLKOUT

↑ to

ns

serial bit position 3

Delay time, CLKOUT

↑ to

serial bit position 4

Delay time, CLKOUT

↑ to

serial bit position 5

Delay time, CLKOUT

↑ to

serial bit position 6

–0.2

0.2

ns

2.7

See Figure 6

Delay time, CLKIN

↓ to

ns

CLKOUT

↑

1

4.5

See Figure 6

±62

See Figure 7

Cycle time, output clock

ps

±121

See Figure 7

Pulse duration, high-level

ns

output clock

Transition time,

differential output voltage

See Figure 3

700

1500

ps

Enable time, SHTDN

↑ to

See Figure 8

1

ms

phase lock (Yn valid)

Disable time, SHTDN

↓ to

See Figure 9

6.5

ns

off state (CLKOUT low)

(1)

(2)

|Input clock jitter| is the magnitude of the change in the input clock period.

(3)

Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15000 cycles.

Copyright © 2006–2008, Texas Instruments Incorporated

Submit Documentation Feedback

5

Product Folder Link(s): SN65LVDS84AQ-Q1