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SN65LVDS95-Q1 Datasheet(PDF) 10 Page - Texas Instruments |
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SN65LVDS95-Q1 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 14 page SN65LVDS95Q1 LVDS SERDES TRANSMITTER SGLS207A − OCTOBER 2003 − REVISED MAY 2008 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 APPLICATION INFORMATION 16-bit bus extension In a 16-bit bus application (Figure 10), TTL data and clock coming from bus transceivers that interface the backplane bus arrive at the Tx parallel inputs of the LVDS serdes transmitter. The clock associated with the bus is also connected to the device. The on-chip PLL synchronizes this clock with the parallel data at the input. The data is then multiplexed into three different line drivers which perform the TTL to LVDS conversion. The clock is also converted to LVDS and presented to a separate driver. This synchronized LVDS data and clock at the receiver, which recovers the LVDS data and clock, performs a conversion back to TTL. Data is then demultiplexed into a parallel format. An on-chip PLL synchronizes the received clock with the parallel data, and then all are presented to the parallel output port of the receiver. SN74FB2032 8 D0−D7 8 D8−D15 SN65LVDS95 LVDS Interface 0 To 10 Meters (Media Dependent) TTL Interface 16-Bit BTL Bus Interface CLK Backplane Bus 8 D0−D7 8 D8−D15 CLK Backplane Bus TTL Interface 16-Bit BTL Bus Interface XMIT Clock RCV Clock SN74FB2032 SN65LVDS96 SN74FB2032 SN74FB2032 Figure 10. 16-Bit Bus Extension 16-bit bus extension with parity In the previous application we did not have a checking bit that would provide assurance that the data crosses the link. If we add a parity bit to the previous example, we would have a diagram similar to the one in Figure 11. The device following the SN74FB2032 is a low cost parity generator. Each transmit-side transceiver/parity generator takes the LVTTL data from the corresponding transceiver, performs a parity calculation over the byte, and then passes the bits with its calculated parity value on the parallel input of the LVDS serdes transmitter. Again, the on-chip PLL synchronizes this transmit clock with the eighteen parallel bits (16 data + 2 parity) at the input. The synchronized LVDS data/parity and clock arrive at the receiver. The receiver performs the conversion from LVDS to LVTTL and the transceiver/parity generator performs the parity calculations. These devices compare their corresponding input bytes with the value received on the parity bit. The transceiver/parity generator will assert its parity error output if a mismatch is detected. |
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