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MC100E136 Datasheet(PDF) 8 Page - ON Semiconductor |
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MC100E136 Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 12 page MC10E136, MC100E136 http://onsemi.com 8 Figure 4. Look-Ahead-Carry Input Structure ACTIVE LOW CLK CIN CLIN Q D Note from the waveforms that the look-ahead-carry output (CLOUT) pulses low one clock pulse before the counter reaches terminal count. Also note that both CLOUT and the carry out pin (COUT) of the device pulse low for only one clock period. The input structure for look-ahead-carry in (CLIN) and carry in (CIN) is pictured in Figure 2. The CLIN input is registered and then ORed with the CIN input. From the truth table one can see that both the CIN and the CLIN inputs must be in a LOW state for the E136 to be enabled to count (either count up or count down). The CLIN inputs are driven by the CLOUT output of the lowest order E136 and therefore are only asserted for a single clock period. Since the CLIN input is registered it must be asserted one clock period prior to the CIN input. If the counter previous to a given counter is at terminal count its COUT output and thus the CIN input of the given counter will be in the “LOW” state. This signals the given counter that it will need to count one upon the next terminal count of the least significant counter (LSC). The CLOUT output of the LSC will pulse low one clock period before it reaches terminal count. This CLOUT signal will be clocked into the CLIN input of the higher order counters on the following positive clock transition. Since both CIN and CLIN are in the LOW state the next clock pulse will cause the least significant counter to roll over and all higher order counters, if signaled by their CIN inputs, to count by one. Figure 5. 6-bit Programmable Divider “LO” S2 S1 Q0 −> Q5 D0 −> D5 COUT COUT CLK CLOCK During the clock pulse in which the higher order counter is counting by one the CLIN is clocking in the high signal presented by the CLOUT of the LSC. The CIN’s in the higher order counter will ripple propagate through the chain to update the count status for the next occurrence of terminal count on the LSC. This ripple propagation will not affect the count frequency as it has 26−1 or 63 clock pulses to ripple through without affecting the count operation of the chain. The only limiting factor which could reduce the count frequency of the chain as compared to a free running single device will be the setup time of the CLIN input. This limit will consist of the CLK to CLOUT delay of the E136 plus the CLIN setup time plus any path length differences between the CLOUT output and the clock. Programmable Divider Using external feedback of the COUT pin, the E136 can be configured as a programmable divider. Figure 3 illustrates the configuration for a 6-bit count down programmable divider. If for some reason a count up divider is preferred the COUT signal is simply fed back to S2 rather than S1. Examination of the truth table for the E136 shows that when both S1 and S2 are LOW the counter will parallel load on the next positive transition of the clock. If the S2 input is low and the S1 input is high the counter will be in the count down mode and will count towards an all zero state upon successive clock pulses. Knowing this and the operation of the COUT output it becomes a trivial matter to build programmable dividers. For a programmable divider one wants to load a predesignated number into the counter and count to terminal count. Upon terminal count the counter should automatically reload the divide number. With the architecture shown in Figure 3 when the counter reaches terminal count the COUT output and thus the S1 input will go LOW, this combined with the low on S2 will cause the counter to load the inputs present on D0-D5. Upon loading the divide value into the counter COUT will go HIGH as the counter is no longer at terminal count thereby placing the counter back into the count mode. Table 10. Preset Inputs Versus Divide Ratio Divide Preset Data Inputs Ratio D5 D4 D3 D2 D1 D0 2 3 4 5 • • 36 37 38 • • 62 63 64 L L L L • • H H H • • H H H L L L L • • L L L • • H H H L L L L • • L L L • • H H H L L L H • • L H H • • H H H L H H L • • H L L • • L H H H L H L • • H L H • • H L H |
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