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SN74AHC595QPWRQ1 Datasheet(PDF) 5 Page - Texas Instruments

Part No. SN74AHC595QPWRQ1
Description  8-BIT SHIFT REGISTER WITH 3-STATE OUTPUT REGISTERS
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Maker  TI1 [Texas Instruments]
Homepage  http://www.ti.com
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ELECTRICAL CHARACTERISTICS
TIMING REQUIREMENTS
TIMING REQUIREMENTS
SN74AHC595-Q1
8-BIT SHIFT REGISTER
WITH 3-STATE OUTPUT REGISTERS
SCLS537B – AUGUST 2003 – REVISED JANUARY 2008
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX
UNIT
MIN
TYP
MAX
2 V
1.9
2
1.9
IOH = –50 µA
3 V
2.9
3
2.9
VOH
4.5 V
4.4
4.5
4.4
V
IOH = –4 mA
3 V
2.58
2.48
IOH = –8 mA
4.5 V
3.94
3.8
2 V
0.1
0.1
IOL = 50 µA
3 V
0.1
0.1
VOL
4.5 V
0.1
0.1
V
IOL = 4 mA
3 V
0.36
0.44
IOL = 8 mA
4.5 V
0.36
0.44
II
VI = 5.5 V or GND
0 V to 5.5 V
±0.1
±1
µA
QA–QH, VI = VCC or GND,
IOZ
5.5 V
±0.25
±10
µA
VO = VCC or GND, OE = VIH or VIL
ICC
VI = VCC or GND, IO = 0
5.5 V
4
40
µA
Ci
VI = VCC or GND
5 V
3
10
10
pF
Co
VO = VCC or GND
5 V
5.5
pF
VCC = 3.3 V ± 0.3 V, over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
UNIT
MIN
MAX
SRCLK high or low
5.5
6.5
tw
Pulse duration
RCLK high or low
5.5
6.5
ns
SRCLR low
5
6
SER before SRCLK
3.5
4.5
SRCLK
↑ before RCLK↑(1)
8
9.5
tsu
Setup time
ns
SRCLR low before RCLK
8
10
SRCLR high (inactive) before SRCLK
3
4
th
Hold time
SER after SRCLK
1.5
2.5
ns
(1)
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
VCC = 5 V ± 0.5 V, over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
UNIT
MIN
MAX
SRCLK high or low
5
6
tw
Pulse duration
RCLK high or low
5
6
ns
SRCLR low
5.2
6.2
SER before SRCLK
3
4
SRCLK
↑ before RCLK↑(1)
5
6
tsu
Setup time
ns
SRCLR low before RCLK
5
6
SRCLR high (inactive) before SRCLK
2.5
3.5
th
Hold time
SER after SRCLK
2
3
ns
(1)
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
Copyright © 2003–2008, Texas Instruments Incorporated
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