CY7C1353G

Document Number: 38-05515 Rev. *J

Page 7 of 18

Truth Table

The truth table for CY7C1353G follows. [1, 2, 3, 4, 5, 6, 7]

Operation

DQ

Deselect cycle

None

H

X

X

L

L

X

X

X

L

L->H

Tri-state

Deselect cycle

None

X

X

H

L

L

X

X

X

L

L->H

Tri-state

Deselect cycle

None

X

L

X

L

L

X

X

X

L

L->H

Tri-state

Continue deselect cycle

None

X

X

X

L

H

X

X

X

L

L->H

Tri-state

READ cycle (begin burst)

External

L

H

L

L

L

H

X

L

L

L->H Data out (Q)

READ cycle (continue burst)

Next

X

X

X

L

H

X

X

L

L

L->H Data out (Q)

NOP/DUMMY READ (begin burst)

External

L

H

L

L

L

H

X

H

L

L->H

Tri-state

DUMMY READ (continue burst)

Next

X

X

X

L

H

X

X

H

L

L->H

Tri-state

WRITE cycle (begin burst)

External

L

H

L

L

L

L

L

X

L

L->H Data in (D)

WRITE cycle (continue burst)

Next

X

X

X

L

H

X

L

X

L

L->H Data in (D)

NOP/WRITE ABORT (begin burst)

None

L

H

L

L

L

L

H

X

L

L->H

Tri-state

WRITE ABORT (continue burst)

Next

X

X

X

L

H

X

H

X

L

L->H

Tri-state

IGNORE CLOCK EDGE (stall)

Current

X

X

X

L

X

X

X

X

H

L->H

–

SLEEP MODE

None

X

X

X

H

X

X

X

X

X

X

Tri-state

Partial Truth Table for Read/Write

The partial truth table for Read/Write for CY7C1353G follows. [1, 2, 8]

Function

WE

Read

HX

X

Write – no bytes written

LH

H

L

H

H

L

Write all bytes

LL

L

Notes

1. X =”Don’t Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one byte write select is active, BWx = valid signifies that the desired byte write selects

are asserted, see truth table for details.

3. When a write cycle is detected, all IOs are tri-stated, even during byte writes.

5. CEN = H, inserts wait states.

6. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.

8. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write is based on which byte write is active.