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CY7C1353G Datasheet(PDF) 7 Page - Cypress Semiconductor |
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CY7C1353G Datasheet(HTML) 7 Page - Cypress Semiconductor |
7 / 18 page CY7C1353G Document Number: 38-05515 Rev. *J Page 7 of 18 Truth Table The truth table for CY7C1353G follows. [1, 2, 3, 4, 5, 6, 7] Operation Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK DQ Deselect cycle None H X X L L X X X L L->H Tri-state Deselect cycle None X X H L L X X X L L->H Tri-state Deselect cycle None X L X L L X X X L L->H Tri-state Continue deselect cycle None X X X L H X X X L L->H Tri-state READ cycle (begin burst) External L H L L L H X L L L->H Data out (Q) READ cycle (continue burst) Next X X X L H X X L L L->H Data out (Q) NOP/DUMMY READ (begin burst) External L H L L L H X H L L->H Tri-state DUMMY READ (continue burst) Next X X X L H X X H L L->H Tri-state WRITE cycle (begin burst) External L H L L L L L X L L->H Data in (D) WRITE cycle (continue burst) Next X X X L H X L X L L->H Data in (D) NOP/WRITE ABORT (begin burst) None L H L L L L H X L L->H Tri-state WRITE ABORT (continue burst) Next X X X L H X H X L L->H Tri-state IGNORE CLOCK EDGE (stall) Current X X X L X X X X H L->H – SLEEP MODE None X X X H X X X X X X Tri-state Partial Truth Table for Read/Write The partial truth table for Read/Write for CY7C1353G follows. [1, 2, 8] Function WE BWA BWB Read HX X Write – no bytes written LH H Write byte A – (DQA and DQPA)L L H Write byte B – (DQB and DQPB)L H L Write all bytes LL L Notes 1. X =”Don’t Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one byte write select is active, BWx = valid signifies that the desired byte write selects are asserted, see truth table for details. 2. Write is defined by BWX, and WE. See truth table for read/write. 3. When a write cycle is detected, all IOs are tri-stated, even during byte writes. 4. The DQs and DQP[A:B] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. CEN = H, inserts wait states. 6. Device powers up deselected and the IOs in a tri-state condition, regardless of OE. 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:B] = tri-state when OE is inactive or when the device is deselected, and DQs and DQP[A:B] = data when OE is active. 8. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write is based on which byte write is active. |
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Similar Description - CY7C1353G_12 |
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