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CY7C65632-28LTXCT Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY7C65632-28LTXCT Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 25 page  CY7C65632, CY7C65634 HX2VL™ Very Low Power USB 2.0 Hub Controller Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-67568 Rev. *F Revised July 2, 2012 HX2VL™ Very Low Power USB 2.0 Hub Controller Features ■ High performance, low-power USB 2.0 Hub, optimized for low cost designs with minimum Bill-of-material ■ USB 2.0 hub controller ❐ Compliant with USB 2.0 specification ❐ Up to four downstream ports support ❐ Downstream ports are backward compatible with FS, LS ❐ Single transaction translator (TT) for low cost ■ Very low power consumption ❐ Supports bus-powered and self-powered modes ❐ Auto switching between bus-powered and self-powered ❐ Single MCU with 2K ROM and 64 byte RAM ❐ Lowest power consumption ■ Highly integrated solution for reduced BOM cost ❐ Internal regulator – single power supply 5 V required ❐ Provision of connecting 3.3 V with external regulator ❐ Integrated upstream pull-up resistor ❐ Integrated pull-down resistors for all downstream ports ❐ Integrated upstream/downstream termination resistors ❐ Integrated port status indicator control ❐ 12 MHz +/– 500 ppm external crystal with drive level 600 µW (integrated PLL) clock input with optional 27/48 MHz oscillator clock input ❐ Internal power failure detection for ESD recovery ■ Downstream port management ❐ Support individual and ganged mode power management ❐ Overcurrent detection ❐ Two port status indicators per downstream port ❐ Slew rate control for EMI management ■ Maximum configurability ❐ VID and PID are configurable through external EEPROM ❐ Number of ports, removable/non-removable ports are configurable through EEPROM and I/O pin configuration ❐ I/O pins can configure gang/individual mode power switching, reference clock source and polarity of power switch enable pin ❐ Configuration options also available through mask ROM ■ Available in space saving 48-pin (7 × 7 mm) TQFP and 28-pin (5 × 5 mm) QFN packages ■ Supports 0 °C to 70 °C temperature range D+ D- 3.3V i/p (with ext. reg. & 28 QFN) NC (with ext. reg. & 48 TQFP) 3.3V o/p (for int. reg.) Hub Repeater Routing Logic USB Downstream Port 1 USB 2.0 PHY Port Control USB Downstream Port 2 USB 2.0 PHY Port Control USB Downstream Port 3 USB 2.0 PHY Port Control USB Downstream Port 4 USB 2.0 PHY Port Control MCU RAM ROM USB Upstream Port USB 2.0 PHY PLL D+ D- LED D+ D- LED D+ D- LED D+ D- LED I2C / SPI 12/27/48 MHz OSC-in OR 12 MHz Crystal Transaction Translator Regulator 1.8V Serial Interface Engine HS USB Control Logic 3.3V 5V i/p (for internal regulator) NC (for external regulator) For two port version, USB Downstream ports 3 and 4 are to be No connect from the Chip I/O perspective. Block Diagram – CY7C6563X |
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