CY7C65632, CY7C65634

Document Number: 001-67568 Rev. *F

Page 10 of 25

Pin Definitions

48-pin TQFP Package

Name

Pin No.

Type [1]

Description

Power and Clock

VCC_A

1

P

VCC_A

7

P

VCC_A

12

P

VCC_A

16

P

VCC_A

19

P

VCC_D

34

P

VCC_D

38

P

VCC

47

P

VREG

48

P

GND

2

P

GND. Connect to Ground with as short a path as possible.

GND

8

P

GND. Connect to Ground with as short a path as possible.

GND

13

P

GND. Connect to Ground with as short a path as possible.

GND

20

P

GND. Connect to Ground with as short a path as possible.

XIN

14

I

12 MHz crystal clock input, or 12/27/48 MHz clock input.

XOUT

15

O

12 MHz Crystal OUT

SEL48/SEL27

25 / 44

I

Clock source selection inputs.

00: Reserved

01: 48 MHz OSC-in

10: 27 MHz OSC-in

11: 12 MHz Crystal or OSC-in

RESET#

26

I

Active LOW Reset. External reset input, default pull high 10 k

; When RESET = low,

whole chip is reset to the initial state.

SELFPWR

37

I

Self Power. Input for selecting self/bus power. 0 is bus powered, 1 is self powered.

GANG

39

I/O

GANG. Default is input mode after power-on-reset.

Gang Mode: Input:1 -> Output is 0 for Normal Operation and 1 for Suspend

Individual Mode: Input:0 -> Output is 1 for Normal Operation and 0 for Suspend

Refer to Gang/Individual Power Switching Modes in Pin Configuration Options

Section for details

RREF

11

I/O

649 ohm resistor must be connected between RREF and Ground.

System Interface

Test

I2C_SCL

27

Test: 0: Normal Operation & 1: Chip will be put in test mode.

I2C_SCL: Can be used as I2C clock pin to access I2C EEPROM.

Upstream Port

D–

3

I/O/Z

Upstream D– Signal.

D+

4

I/O/Z

Upstream D+ Signal.

Downstream Port 1

DD–[1]

5

I/O/Z

Downstream D– Signal. Downstream D- signal of port 1.

DD+[1]

6

I/O/Z

Downstream D+ Signal. Downstream D+ signal of port 1.

AMBER[1]

SPI_CS

46

LED. Driver output for Amber LED. Port Indicator Support. Default is Active LOW.

SPI_CS. Can be used as chip select to access external SPI EEPROM.

Note