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CY14B104M-ZSP25XIT Datasheet(PDF) 1 Page - Cypress Semiconductor |
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CY14B104M-ZSP25XIT Datasheet(HTML) 1 Page - Cypress Semiconductor |
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1 / 34 page  CY14B104K, CY14B104M 4-Mbit (512 K × 8/256 K × 16) nvSRAM with Real Time Clock Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 001-07103 Rev. *Z Revised August 27, 2012 4-Mbit (512 K × 8/256 K × 16) nvSRAM with Real Time Clock Features ■ 25 ns and 45 ns access times ■ Internally organized as 512 K × 8 (CY14B104K) or 256 K × 16 (CY14B104M) ■ Hands off automatic STORE on power-down with only a small capacitor ■ STORE to QuantumTrap nonvolatile elements is initiated by software, device pin, or AutoStore on power-down ■ RECALL to SRAM is initiated by software or power-up ■ High reliability ■ Infinite read, write, and RECALL cycles ■ 1 million STORE cycles to QuantumTrap ■ 20 year data retention ■ Single 3 V +20%, –10% operation ■ Data integrity of Cypress nvSRAM combined with full-featured real time clock (RTC) ■ Watchdog timer ■ Clock alarm with programmable interrupts ■ Capacitor or battery backup for RTC ■ Industrial temperature ■ 44-pin and 54-pin thin small outline package (TSOP) Type II ■ Pb-free and restriction of hazardous substances (RoHS) compliant Functional Description The Cypress CY14B104K and CY14B104M combines a 4-Mbit nonvolatile static RAM (nvSRAM) with a full-featured RTC in a monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM is read and written infinite number of times, while independent nonvolatile data resides in the nonvolatile elements. The RTC function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The alarm function is programmable for periodic minutes, hours, days, or months alarms. There is also a programmable watchdog timer for process control. STATIC RAM ARRAY 2048 X 2048 R O W D E C O D E R COLUMN I/O COLUMN DEC I N P U T B U F F E R S POWER CONTROL STORE/RECALL CONTROL Quatrum Trap 2048 X 2048 STORE RECALL V CC V CA P HSB A 9 A10 A11 A12 A13 A14 A15 A16 SOFTWARE DETECT A 14 - A2 OE CE WE BHE BLE A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 17 A 18 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 RTC MUX A 18- A0 X out X in INT V RTCbat V RTCcap Logic Block Diagram [1, 2, 3] Notes 1. Address A0–A18 for × 8 configuration and Address A0–A17 for × 16 configuration. 2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration. 3. BHE and BLE are applicable for × 16 configuration only. |
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