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CY14B256KA-SP45XIT Datasheet(PDF) 8 Page - Cypress Semiconductor |
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CY14B256KA-SP45XIT Datasheet(HTML) 8 Page - Cypress Semiconductor |
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8 / 27 page  CY14B256KA Document Number: 001-55720 Rev. *G Page 8 of 27 During backup operation, the CY14B256KA consumes a 0.35 µA (Typ) at room temperature. The user must choose capacitor or battery values according to the application. Backup time values based on maximum current specifications are shown in the following Table 2. Nominal backup times are approximately two times longer. Using a capacitor has the obvious advantage of recharging the backup source each time the system is powered up. If a battery is used, a 3 V lithium is recommended and the CY14B256KA sources current only from the battery when the primary power is removed. However, the battery is not recharged at any time by the CY14B256KA. The battery capacity must be chosen for total anticipated cumulative down time required over the life of the system. Stopping and Starting the Oscillator The OSCEN bit in the calibration register at 0x7FF8 controls the enable and disable of the oscillator. This bit is nonvolatile and is shipped to customers in the “enabled” (set to ‘0’) state. To preserve the battery life when the system is in storage, OSCEN must be set to ‘1’. This turns off the oscillator circuit, extending the battery life. If the OSCEN bit goes from disabled to enabled, it takes approximately one second (two seconds maximum) for the oscillator to start. While system power is off, if the voltage on the backup supply (VRTCcap or VRTCbat) falls below their respective minimum level, the oscillator may fail.The CY14B256KA has the ability to detect oscillator failure when system power is restored. This is recorded in the Oscillator Fail Flag (OSCF) of the flags register at the address 0x7FF0. When the device is powered on (VCC goes above VSWITCH) the OSCEN bit is checked for the ‘enabled’ status. If the OSCEN bit is enabled and the oscillator is not active within the first 5 ms, the OSCF bit is set to ‘1’. The system must check for this condition and then write ‘0’ to clear the flag. Note that in addition to setting the OSCF flag bit, the time registers are reset to the ‘Base Time’, which is the value last written to the timekeeping registers. The control or calibration registers and the OSCEN bit are not affected by the ‘oscillator failed’ condition. The value of OSCF must be reset to ‘0’ when the time registers are written for the first time. This initializes the state of this bit which may have become set when the system was first powered on. To reset OSCF, set the write bit ‘W’ (in the flags register at 0x7FF0) to a ‘1’ to enable writes to the flags register . Write a ‘0’ to the OSCF bit and then reset the write bit to ‘0’ to disable writes. Calibrating the Clock The RTC is driven by a quartz controlled crystal with a nominal frequency of 32.768 kHz. Clock accuracy depends on the quality of the crystal and calibration. The crystals available in market typically have an error of +20 ppm to +35 ppm. However, CY14B256KA employs a calibration circuit that improves the accuracy to +1/–2 ppm at 25 °C. This implies an error of +2.5 seconds to –5 seconds per month. The calibration circuit adds or subtracts counts from the oscillator divider circuit to achieve this accuracy. The number of pulses that are suppressed (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in Calibration register at 0x7FF8. The calibration bits occupy the five lower order bits in the Calibration register. These bits are set to represent any value between ‘0’ and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates positive calibration and a ‘0’ indicates negative calibration. Adding counts speeds the clock up and subtracting counts slows the clock down. If a binary ‘1’ is loaded into the register, it corresponds to an adjustment of 4.068 or –2.034 ppm offset in oscillator error, depending on the sign. Calibration occurs within a 64-minute cycle. The first 62 minutes in the cycle may, once every minute, have one second shortened by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is loaded into the register, only the first two minutes of the 64-minute cycle are modified. If a binary 6 is loaded, the first 12 are affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm of adjustment per calibration step in the Calibration register. To determine the required calibration, the CAL bit in the flags register (0x7FF0) must be set to ‘1’. This causes the INT pin to toggle at a nominal frequency of 512 Hz. Any deviation measured from the 512 Hz indicates the degree and direction of the required correction. For example, a reading of 512.01024 Hz indicates a +20 ppm error. Hence, a decimal value of –10 (001010b) must be loaded into the Calibration register to offset this error. Note Setting or changing the Calibration register does not affect the test output frequency. To set or clear CAL, set the write bit ‘W’ (in the flags register at 0x7FF0) to ‘1’ to enable writes to the flags register . Write a value to CAL, and then reset the write bit to ‘0’ to disable writes. Alarm The alarm function compares user programmed values of alarm time and date (stored in the registers 0x7FF1-5) with the corre- sponding time of day and date values. When a match occurs, the alarm internal flag (AF) is set and an interrupt is generated on INT pin if Alarm Interrupt Enable (AIE) bit is set. There are four alarm match fields – date, hours, minutes, and seconds. Each of these fields has a match bit that is used to determine if the field is used in the alarm match logic. Setting the match bit to ‘0’ indicates that the corresponding field is used in the match process. Depending on the match bits, the alarm occurs as specifically as once a month or as frequently as once every minute. Selecting none of the match bits (all 1s) indicates that no match is required and therefore, alarm is disabled. Selecting all match bits (all 0s) causes an exact time and date match. There are two ways to detect an alarm event: by reading the AF flag or monitoring the INT pin. The AF flag in the flags register at 0x7FF0 indicates that a date or time match has occurred. The AF bit is set to ‘1’ when a match occurs. Reading the flags Table 2. RTC Backup Time Capacitor Value Backup Time 0.1 F 72 hours 0.47 F 14 days 1.0 F 30 days |
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