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CY14ME064J1A-SXIT Datasheet(PDF) 6 Page - Cypress Semiconductor |
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CY14ME064J1A-SXIT Datasheet(HTML) 6 Page - Cypress Semiconductor |
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6 / 28 page  PRELIMINARY CY14MB064J1A/CY14MB064J2A CY14ME064J1A/CY14ME064J2A Document Number: 001-70393 Rev. *E Page 6 of 28 High Speed Mode (Hs-mode) In Hs-mode, nvSRAM can transfer data at bit rates of up to 3.4 Mbit/s. A master code (0000 1XXXb) must be issued to place the device into high speed mode. This enables master/slave communication for speed upto 3.4 MHz. A stop condition exits Hs-mode. Serial Data Format in Hs-mode Serial data transfer format in Hs-mode meets the standard-mode I2C-bus specification. Hs-mode can only commence after the following conditions (all of which are in F/S-modes): 1. START condition (S) 2. 8-bit master code (0000 1XXXb) 3. No-acknowledge bit (A) Single and multiple-byte reads and writes are supported. After the device enters into Hs-mode, data transfer continues in Hs-mode until stop condition is sent by master device. The slave switches back to F/S-mode after a STOP condition (P). To continue data transfer in Hs-mode, the master sends Repeated START (Sr). See Figure 12 on page 11 and Figure 15 on page 12 for Hs-mode timings for read and write operation. Slave Device Address Every slave device on an I2C bus has a device select address. The first byte after START condition contains the slave device address with which the master intends to communicate. The seven MSBs are the device address and the LSB (R/W bit) is used for indicating Read or Write operation. The CY14MX064J reserves two sets of upper 4 MSBs [7:4] in the slave device address field for accessing Memory and Control Registers. The accessing mechanism is described in Memory Slave Device on page 7. The nvSRAM product provides two different functionalities: Memory and Control Registers functions (such as serial number and product ID). The two functions of the device are accessed through different slave device addresses. The first four most significant bits [7:4] in the device address register are used to select between the nvSRAM functions. Figure 5. Acknowledge on the I2C Bus handbook, full pagewidth S START condition 9 8 2 1 clock pulse for acknowledgement not acknowledge (A) acknowledge (A) DATA OUTPUT BY MASTER DATA OUTPUT BY SLAVE SCL FROM MASTER Figure 6. Data transfer format in Hs-mode handbook, full pagewidth F/S-mode Hs-mode F/S-mode AA / A A DATA n (bytes +ack.) W / R S MASTER CODE Sr SLAVE ADD. Hs-mode continues Sr SLAVE ADD. P |
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