Document Number: 38-05576 Rev. *O

Page 8 of 18

Switching Waveforms

Figure 3. Read Cycle No. 1 (Address Transition Controlled) [22, 23]

Figure 4. Read Cycle No. 2 (OE Controlled) [23, 24]

Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [25, 26]

PREVIOUS DATA VALID

DATA VALID

RC

ADDRESS

DATA OUT

50%

50%

DATA VALID

HIGH IMPEDANCE

IMPEDANCE

HIGH

ADDRESS

CE

DATA OUT

SUPPLY

CURRENT

OE

DATA VALID

ADDRESS

CE

WE

DATA I/O

OE

NOTE 27

Notes

23. WE is HIGH for read cycles.

24. Address valid before or similar to CE transition LOW.

26. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.

27. During this period, the I/Os are in output state. Do not apply input signals.