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MSP430F5309IRGC Datasheet(PDF) 10 Page - Texas Instruments |
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MSP430F5309IRGC Datasheet(HTML) 10 Page - Texas Instruments |
10 / 100 page MSP430F530x, MSP430F5310 SLAS677C – SEPTEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com Table 3. Terminal Functions TERMINAL NO. I/O(1) DESCRIPTION NAME RGZ, RGC ZQE PT General-purpose digital I/O P6.4/CB4/A4 5 N/A C1 I/O Comparator_B input CB4 (not available on RGZ or PT package devices) Analog input A4 – ADC (not available on RGZ or PT package devices) General-purpose digital I/O P6.5/CB5/A5 6 N/A D2 I/O Comparator_B input CB5 (not available on RGZ or PT package devices) Analog input A5 – ADC (not available on RGZ or PT package devices) General-purpose digital I/O P6.6/CB6/A6 7 N/A D1 I/O Comparator_B input CB6 (not available on RGZ or PT package devices) Analog input A6 – ADC (not available on RGZ or PT package devices) General-purpose digital I/O P6.7/CB7/A7 8 N/A D3 I/O Comparator_B input CB7 (not available on RGZ or PT package devices) Analog input A7 – ADC (not available on RGZ or PT package devices) General-purpose digital I/O P5.0/A8/VeREF+ 9 5 E1 I/O Analog input A8 – ADC Input for an external reference voltage to the ADC General-purpose digital I/O P5.1/A9/VeREF- 10 6 E2 I/O Analog input A9 – ADC Negative terminal for an externally provided ADC reference AVCC1 11 7 F2 Analog power supply General-purpose digital I/O P5.4/XIN 12 8 F1 I/O Input terminal for crystal oscillator XT1 General-purpose digital I/O P5.5/XOUT 13 9 G1 I/O Output terminal of crystal oscillator XT1 AVSS1 14 10 G2 Analog ground supply DVCC1 15 11 H1 Digital power supply DVSS1 16 12 J1 Digital ground supply Regulated core power supply output (internal use only, no external current VCORE(2) 17 13 J2 loading) General-purpose digital I/O with port interrupt P1.0/TA0CLK/ACLK 18 14 H2 I/O TA0 clock signal TA0CLK input ACLK output (divided by 1, 2, 4, 8, 16, or 32) General-purpose digital I/O with port interrupt P1.1/TA0.0 19 15 H3 I/O TA0 CCR0 capture: CCI0A input, compare: Out0 output BSL transmit output General-purpose digital I/O with port interrupt P1.2/TA0.1 20 16 J3 I/O TA0 CCR1 capture: CCI1A input, compare: Out1 output BSL receive input General-purpose digital I/O with port interrupt P1.3/TA0.2 21 17 G4 I/O TA0 CCR2 capture: CCI2A input, compare: Out2 output General-purpose digital I/O with port interrupt P1.4/TA0.3 22 18 H4 I/O TA0 CCR3 capture: CCI3A input compare: Out3 output General-purpose digital I/O with port interrupt P1.5/TA0.4 23 19 J4 I/O TA0 CCR4 capture: CCI4A input, compare: Out4 output General-purpose digital I/O with port interrupt P1.6/TA1CLK/CBOUT 24 20 G5 I/O TA1 clock signal TA1CLK input Comparator_B output General-purpose digital I/O with port interrupt P1.7/TA1.0 25 21 H5 I/O TA1 CCR0 capture: CCI0A input, compare: Out0 output General-purpose digital I/O with port interrupt P2.0/TA1.1 26 22 J5 I/O TA1 CCR1 capture: CCI1A input, compare: Out1 output (1) I = input, O = output, N/A = not available (2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended capacitor value, CVCORE. 10 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated |
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