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CXD2053AS Datasheet(PDF) 11 Page - Sony Corporation |
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CXD2053AS Datasheet(HTML) 11 Page - Sony Corporation |
11 / 14 page – 11 – CXD2053AM/AS 6. Processing of EDTV-II ID and ID-1 data from the bus EDTV-II ID or ID-1 EDVLD or VBVLD Decoder Data validity judgment I2C CXD2053AM/AS Pin direct output to microcomputer As shown in the figure above, the data validity judgment and decoding results are obtained independently during EDTV-II ID or ID-1 decoding. When outputting these results directly to pins, the results are output after first taking their logical product (AND). These results are output independently to the I2C bus. Therefore, processing inside the microcomputer which has acquired the information from the I2C is performed either by simply outputting this data directly to the pins or by taking the logical product (AND) as above. In addition, performing the processing when the data validity judgment result (EDVLD or VBVLD) is 1 and the decoding result is 0 allows video to be judged as 4:3 video. Even video which has had the top and bottom of the screen blacked out due to picture composition intentions can be viewed as the original 4:3 video by giving this judgment priority over the auto wide function. 7. Setting EDTV-II ID decoding function The performance of the EDTV-II ID decoding function can be switched directly by pin settings during either I2C bus or bus-free mode. Setting I2C exists I2C -free Resistance to ghosting Resistance to weak electric fields ED2FSC = 0 EDDEC2 bit3 = 0, bit2 = 1 SCL (15pin) = Low SDA (16pin) = Low Medium Medium ED2FSC = 0 EDDEC2 bit3 = 1, bit2 = 0 SCL (15pin) = High SDA (16pin) = Low Strong Medium ED2FSC = 1 EDDEC2 bit3 = 1, bit2 = 0 SCL (15pin) = High SDA (15pin) = High Strong Strong Table 5. EDTV-II ID decoding function switching ED2FSC is originally a function which stops the 3.58MHz amplitude check for the Y signal input from the S terminal, etc. However, it can also be used in combination with the EDDEC2 setting to increase the resistance to ghosting and weak electric fields as shown in the table above. EDDEC2 is the luminance check level switching during the 3.58MHz or 2.04MHz confirmation signal interval. Similarly, although EDDEC1 is the 2.04MHz amplitude check level switching, it should be set to bit 5 = 0 and bit 4 = 1. Since EDTV-II ID identification for this IC is simple identification, increasing the resistance to weak electric fields, etc. results in a tradeoff which increases the possibility of misoperation. Accordingly, the leftmost settings in the table above should be used as the standard settings, and other settings used only when necessary. |
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