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CXD2300Q Datasheet(PDF) 8 Page - Sony Corporation |
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CXD2300Q Datasheet(HTML) 8 Page - Sony Corporation |
8 / 14 page —8— CXD2300Q DC characteristics (Fc = 18MSPS, VDD = 3.3 V, VRB = 0 V, VRT = 1.5 V, Ta = 25 °C) Supply current Reference pin current Analog input capacitance Reference resistance (VRT to VRB) Self-bias Digital input voltage Digital input current Digital output current IDD IREF CIN RREF VRB1 VRT1 – VRB1 VIH VIL IIH IIL IOH IOL IOZH IOZL 3.3 230 0.33 1.30 2.5 –1.0 3.3 Fc = 18MSPS NTSC ramp wave input VIN = 0.75 V + 0.07 Vrms Shorts VRB and VRBS Shorts VRT and VRTS VDD = 3.14 to 3.6 V Ta = –40 to +85 °C VDD = max OE = VSS VDD = min OE = VDD VDD = max 5.5 4.6 8 330 0.36 1.39 10 6.6 440 0.39 1.48 0.5 5 5 16 16 mA mA pF Ω V V µA mA µA Item Symbol Conditions Min. Typ. Max. Unit Timing (Fc = 18MSPS, VDD = 3. 3V, VRB = 0 V, VRT = 1.5 V, Ta = 25 °C) Output data delay Tri-state output enable time Tri-state output disable time Clamp pulse width∗1 TDL tPZH tPZL tPHZ tPLZ tcpw 8 6 4 1.75 With TTL 1 gate and 10pF load VDD = 3.14 to 3.6 V Ta = –40 to +85 °C RL = 1 k Ω, CL = 20 pF OE = 3 V → 0 V VDD = 3.14 to 3.6 V Ta = –40 to +85°C RL = 1 k Ω, CL = 20 pF OE = 0 V → 3 V VDD = 3.14 to 3.6 V Ta = –40 to +85 °C Fc = 14.3MSPS, CIN = 10 µF for NTSC wave 18 12 7.5 2.75 30 25 16 3.75 ns ns ns µs Item Symbol Conditions Min. Typ. Max. Unit VIH = VDD VIL = 0 V VOH = VDD – 0.5 V VOL = 0.4 V VOH = VDD VOL = 0 V ∗1 The clamp pulse width is for NTSC as an example. Adjust the rate to the clamp pulse cycle (1/15.75 kHz for NTSC) for other processing systems to equal the values for NTSC. |
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