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IS61DDPB44M18A Datasheet(PDF) 4 Page - Integrated Silicon Solution, Inc |
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IS61DDPB44M18A Datasheet(HTML) 4 Page - Integrated Silicon Solution, Inc |
4 / 32 page IS61DDPB44M18A/A1/A2 IS61DDPB42M36A/A1/A2 Integrated Silicon Solution, Inc.- www.issi.com Rev. 00A 7/05/2012 4 SRAM Features Description Block Diagram Data Register Burst4 Control Logic 19(20) Addresses 4(2) LD# R/W# BWx# Clock Generator K K# 2M x 36 (4M x 18) Memory Array Write Driver Select Output Control 19(20) 36x4(18x4) 36x4(18x4) 36x4 (18x4) 36 (18) DQ(Data-out &Data-In) CQ, CQ# (Echo Clocks) /Doff Add Reg & Burst Control 144 (72) Output Reg 36 (18) 36(18) QVLD Note: Numerical values in parentheses refer to the x18 device configuration . Read Operations The SRAM operates continuously in a burst-of-four mode. Read cycles are started by registering R/W# in active high state at the rising edge of the K clock. K and K#, are also used to control the timing to the outputs. The data corresponding to the first address is clocked two and half cycles later by the rising edge of the K# clock. The data corresponding to the second burst is clocked three cycles later by the following rising edge of the K clock. A set of free- running echo clocks, CQ and CQ#, are produced internally with timings identical to the data-outs. The echo clocks can be used as data capture clocks by the receiver device. Whenever LD# is low, a new address is registered at the rising edge of the K clock. A NOP operation (LD# is high) does not terminate the previous read. The output drivers disable automatically to a high-Z state. Write Operations Write operations can also be initiated at every other rising edge of the K clock whenever R/W# is low. The write address is also registered at that time. When the address needs to change, LD# needs to be low simultaneously to be registered by the rising edge of K. Again, the write always occurs in bursts of four. Because of its common I/O architecture, the data bus must be tri-stated at least one cycle before the new data-in is presented at the DQ bus. The write data is provided in a ‘late write’ mode; that is, the data-in corresponding to the first address of the burst, is presented one cycle later or at the rising edge of the following K clock. The data-in corresponding to the second write burst address follows next, registered by the rising edge of K#. |
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