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CXD2443Q Datasheet(PDF) 5 Page - Sony Corporation |
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CXD2443Q Datasheet(HTML) 5 Page - Sony Corporation |
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5 / 57 page  – 5 – CXD2443Q ∗ H: Pull up, L: Pull down 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 RSTR WCK RSTW CKO4 CKI4 RPD4 FPD4 VDD VSS PEO4 PWM4 TC4 TC2 FPD2 PEO2 PWM2 RPD2 CKO2 CKI2 VSS CKO3 CKI3 RPD3 PEO3 PWM3 FPD3 TC3 CKSL CKI5 HDR O O O I/O I O O — — I/O O I/O I/O O I/O O O I/O I — I/O I O I/O O O I/O I I O Read reset output (for line buffer, negative polarity) Write clock output (for line buffer) Write reset output (for line buffer, negative polarity) Oscillation cell 4 output (line double-speed controller) Oscillation cell 4 input (line double-speed controller) Phase comparator 4 output (line double-speed controller) Phase comparator 4 output (line double-speed controller) Power supply GND Loop filter integrator 4 output (line double-speed controller) Loop filter integrator 4 input (line double-speed controller) FPD4 output pulse width adjustment (line double-speed controller) FPD2 output pulse width adjustment (NTSC/PAL 16:9) Phase comparator 2 output (NTSC/PAL 16:9) Loop filter integrator 2 output (NTSC/PAL 16:9) Loop filter integrator 2 input (NTSC/PAL 16:9) Phase comparator 2 output (NTSC/PAL 16:9) Oscillation cell 2 output (NTSC/PAL 16:9) Oscillation cell 2 input (NTSC/PAL 16:9) GND Oscillation cell 3 output (HD) Oscillation cell 3 input (HD) Phase comparator 3 output (HD) Loop filter integrator 3 output (HD) Loop filter integrator 3 input (HD) Phase comparator 3 output (HD) FPD3 output pulse width adjustment (HD) PLL system switching (High: Built-in PLL, Low: External PLL) External clock input (for external phase comparison) Phase comparator output (for external phase comparison) — — — — — — — — — — — — — — — — — — — — — — — — — — — H — — Pin No. Symbol I/O Description Input pin for open status |
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