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ERJ-3EKF3922V Datasheet(PDF) 4 Page - International Rectifier |
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ERJ-3EKF3922V Datasheet(HTML) 4 Page - International Rectifier |
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4 / 45 page  - 4 - AUGUST 08, 2012 | DATA SHEET | Rev 3.3 4 IR3898 6A Highly Integrated SupIRBuckTM Single-Input Voltage, Synchronous Buck Regulator PD-97662 PIN DESCRIPTIONS PIN # PIN NAME PIN DESCRIPTION 1 Fb Inverting input to the error amplifier. This pin is connected to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. 2 Vref Internal reference voltage, it can be used for margining operation also. In normal and sequencing mode operation, Vref is left floating. A 1nF ceramic capacitor is recommended between this pin and Gnd. In tracking mode operation, Vref should be tied to Gnd. 3 Comp Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to Fb to provide loop compensation. 4 Gnd Signal ground for internal reference and control circuitry. 5 Rt/Sync Multi-function pin to set switching frequency. Use an external resistor from this pin to Gnd to set the free-running switching frequency. Or use an external clock signal to connect to this pin through a diode, the device’s switching frequency is synchronized with the external clock. 6 S_Ctrl Soft start/stop control. A high logic input enables the device to go into the internal soft start; a low logic input enables the output soft discharged. Pull this pin high if this function is not used. 7 PGood Power Good status pin. Output is open drain. Connect a pull up resistor (49.9K) from this pin to the voltage lower than or equal to the Vcc. 8 Vsns Sense pin for over-voltage protection and PGood. It is optional to tie this pin to FB pin directly instead of using a resistor divider from Vout. 9 Vin Input voltage for Internal LDO. A 1.0µF capacitor should be connected between this pin and PGnd. If external supply is connected to Vcc/LDO_out pin, this pin should be shorted to Vcc/LDO_out pin. 10 Vcc/LDO_Out Input Bias for external Vcc Voltage/ output of internal LDO. Place a minimum 2.2µF cap from this pin to PGnd. 11 PGnd Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system’s power ground plane. 12 SW Switch node. This pin is connected to the output inductor. 13 PVin Input voltage for power stage. 14 Boot Supply voltage for high side driver, a 100nF capacitor should be connected between this pin and SW pin. 15 Enable Enable pin to turn on and off the device, if this pin is connected to PVin pin through a resistor divider, input voltage UVLO can be implemented. 16 Vp Input to error amplifier for tracking purposes. In the normal operation, it is left floating and no external capacitor is required. In the sequencing or the tracking mode operation, an external signal can be applied as the reference. 17 Gnd Signal ground for internal reference and control circuitry. |
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