DRV8301

www.ti.com

SLOS719

– AUGUST 2011

GATE TIMING AND PROTECTION CHARACTERISTICS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TIMING, OUTPUT PINS

Positive input falling to GH_x falling

CL=1nF, 50% to 50%

45

ns

Positive input rising to GL_x falling

CL=1nF, 50% to 50%

45

ns

50

ns

Dead Time

50

500

ns

Rise time, gate drive output

CL=1nF, 10% to 90%

25

ns

Fall time, gate drive output

CL=1nF, 90% to 10%

25

ns

Not including handshake communication.

Minimum on pulse

50

ns

Hiz to on state, output of gate driver

Propagation delay matching between high

5

ns

side and low side

Deadtime matching

5

ns

TIMING, PROTECTION AND CONTROL

PVDD is up before start up, all charge

Start up time, from EN_GATE active high

pump caps and regulator caps as in

5

10

ms

to device ready for normal operation

recommended condition

If EN_GATE goes from high to low and

back to high state within quick reset time,

it will only reset all faults and gate driver

Maximum low pulse time

10

us

without powering down charge pump,

current amp, and related internal voltage

regulators.

Delay, error event to all gates low

200

ns

Delay, error event to FAULT low

200

ns

Junction temperature for resetting over

OTW_CLR

115

°C

temperature warning

Junction temperature for over

OTW_SET/OTSD

temperature warning and resetting over

130

°C

_CLR

temperature shut down

Junction temperature for over

OTSD_SET

150

°C

temperature shut down

(1)

Dead time programming definition: Adjustable delay from GH_x falling edge to GL_X rising edge, and GL_X falling edge to GH_X rising

edge. This is a minimum dead-time insertion. It is not added to the value set by the microcontroller externally.

Copyright

© 2011, Texas Instruments Incorporated

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