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IS49NLC18160 Datasheet(PDF) 11 Page - Integrated Silicon Solution, Inc

Part # IS49NLC18160
Description  288Mb (x9, x18, x36) Common I/O RLDRAM 2 Memory
Download  34 Pages
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS49NLC18160 Datasheet(HTML) 11 Page - Integrated Silicon Solution, Inc

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IS49NLC93200,IS49NLC18160,IS49NLC36800
Integrated Silicon Solution, Inc. – www.issi.com –
Rev. 00F, 06/20/2012
11
4.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or the crossing point for
CK/CK#), and parameters specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals
used to test the device is 2V/ns in the range between VIL(AC) and VIH(AC).
5.
The AC and DC input level specifications are as defined in the HSTL Standard (i.e. the receiver will effectively switch as a result of the signal crossing the AC input
level, and will remain in that state as long as the signal does not ring back above[below] the DC input LOW[HIGH] level).
6.
The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross. The input reference level for signal other than CK/CK#
is VREF.
7.
CK and CK# input slew rate must be ≥ 2V/ns (≥ 4V/ns if measured differentially).
8.
VID is the magnitude of the difference between the input level on CK and input level on CK#.
9.
The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same.
10. CK and CK# must cross within the region.
11. CK and CK# must meet at least VID(DC) (MIN.) when static and centered on VDDQ/2.
12. Minimum peak-to-peak swing.


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