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M2S050T-1FG144YES Datasheet(PDF) 10 Page - Microsemi Corporation |
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M2S050T-1FG144YES Datasheet(HTML) 10 Page - Microsemi Corporation |
10 / 156 page SmartFusion2 Device Family Overview 1- 2 R e v ision 0 Reliability SmartFusion2 flash-based fabric has zero FIT configuration rate due to its single event upset (SEU) immunity, which is critical in reliability applications. The flash fabric also has the advantage that no external configuration memory is required, making the device instant-on; it retains configuration when powered off. To complement this unique FPGA capability, SmartFusion2 adds reliability to many other aspects of the device. Single Error Correct Double Error Detect (SECDED) protection is implemented on the Cortex-M3 embedded scratch pad memory, Ethernet, CAN and USB buffers, and is optional on the DDR memory controllers. This means that if a one-bit error is detected, it will be corrected. Errors of more than one bit are detected only and not corrected. SECDED error signals are brought to the FPGA fabric to allow the user to monitor the status of these protected internal memories. Other areas of the architecture are implemented with latches, which are not subject to SEUs. Therefore, no correction is needed in these locations: DDR Bridges (MSS, MDDR, FDDR), Instruction Cache and MMUART, SPI, and PCIe FIFOs. Highest Security Devices Building further on the intrinsic security benefits of flash nonvolatile memory technology, the SmartFusion2 family incorporates essentially all the legacy security features that made the original SmartFusion, Fusion®, IGLOO®, and ProASIC®3 third-generation flash FPGAs and cSoCs the gold standard for secure devices in the PLD industry. In addition, the fourth-generation flash-based SmartFusion2 SoC FPGAs add many unique design and data security features and use models new to the PLD industry. Design Security vs. Data Security When classifying security attributes of programmable logic devices (PLDs), a useful distinction is made between design security and data security. Design Security Design security is protecting the intent of the owner of the design, such as keeping the design and associated bitstream keys confidential, preventing design changes (insertion of Trojan Horses, for example), and controlling the number of copies made throughout the device life cycle. Design security may also be known as intellectual property (IP) protection. It is one aspect of anti-tamper (AT) protection. Design security applies to the device from initial production, includes any updates such as in-the-field upgrades, and can include decommissioning of the device at the end of its life, if desired. Good design security is a prerequisite for good data security. The following are the main design security features supported: • User key and bitstream loading in less-trusted locations – Encrypted key loading using device-unique built-in factory key • Methods to verify devices are programmed correctly, even if done in less-trusted locations • Supply-chain assurances to eliminate counterfeiting • Differential power analysis (DPA) and enhanced anti-tamper features to address non-invasive, semi-invasive, and invasive attacks • Ability to zeroize (destroy) all sensitive stored data in the event of tampering • The M2S080 and M2S120 also have the following features: – Elliptic Curve Cryptography (ECC) for securely loading user keys – An SRAM-type Physically Unclonable Function (SRAM-PUF) for device authentication |
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