CXD3526GG datasheet(11/88 Pages) SONY

Part #	CXD3526GG

Description	Digital Signal Driver/Timing Generator

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Manufacturer	SONY [Sony Corporation]

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CXD3526GG

Description of Operation

1. Description of I/O Pins

(a) System clear pins (XCLR1, XCLR2 and XCLR3)

All internal circuits are initialized by setting XCLR1 (Pin 102) low. In addition, the internal PLL is initialized by

setting XCLR2 (Pin 66) low, and RGB output is initialized (preset) by setting XCLR3 (Pin 103) low.

Initialization should be performed when power is turned on.

(b) Sync signal input pins (HDIN and VDIN)

Horizontal and vertical separate sync signals are input to HDIN (Pin 62) and VDIN (Pin 17), respectively. The

CXD3526GG supports only non-interlace sync signals with a dot clock of 100MHz or less.

(c) Master clock input pins (CLKP/CLKN, CLKC, CLKSEL and CLKPOL)

Phase comparison is performed by an external circuit and a clock synchronized to the sync signal is input. The

master clock input pins have two systems consisting of CLKP/CLKN (Pins 101 and 130) for small-amplitude

differential input (center level: 2.0V, amplitude: ±0.4V), and CLKC (Pin 131) for CMOS level input. In addition,

the clock path selection is performed with CLKSEL (Pin 100) and CLKPOL (Pin 63). The setting values are as

follows.

CLKSEL: 0 = CLKP and CLKN input; 1 = CLKC input

CLKPOL: 0 = Input clock is non-inverted; 1 = Input clock is inverted

(d) PLL setting pin (PLLDIV)

PLLDIV (Pin 129) sets the divider setting of the internal phase compensation PLL circuit. The setting values for

master clock frequency are as follows.

PLLDIV: 0 = 55 to 100MHz; 1 = 27.5 to 55MHz

Note that the frequency of the clock input to the CXD3526GG must be within the phase compensation PLL

operating range, even during free running.

(e) RGB signal input pins (RIN, GIN and BIN)

These pins input RGB digital signals in 10 bits. The Red signal is input to RIN (Pins 4 to 6, 50 to 53 and 89 to

91), the Green signal to GIN (Pins 7, 8, 54, 55, 92, 93 and 123 to 125), and the Blue signal to BIN (Pins 9 to

12, 56 to 58 and 95 to 97) respectively.

(f) OSD signal input pins (ROSD, GOSD, BOSD, YS and YM)

These pins input OSD signals. The Red signal is input to ROSD (Pins 14 and 59), the Green signal to GOSD

(Pins 15 and 60), and the Blue signal to BOSD (Pins 16 and 61) respectively. In addition, the YM signal is input

to YM (Pin 98), and the YS signal to YS (Pin 99).

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