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M2S025S-VF144Y Datasheet(PDF) 2 Page - Microsemi Corporation |
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M2S025S-VF144Y Datasheet(HTML) 2 Page - Microsemi Corporation |
2 / 156 page SmartFusion2 System-on-Chip FPGAs II Re vis i on 0 Microcontroller Subsystem (MSS) • Hard 166 MHz 32-Bit ARM Cortex-M3 Processor – 1.25 DMIPS/MHz – 8 Kbyte Instruction Cache – Embedded Trace Macrocell (ETM) – Memory Protection Unit (MPU) – Single Cycle Multiplication, Hardware Divide – JTAG Debug (4 wires), Serial Wire Debug (SWD, 2 wires), and Serial Wire Viewer (SWV) Interfaces • 64 KB Embedded SRAM (eSRAM) • Up to 512 KB Embedded Nonvolatile Memory (eNVM) • Triple Speed Ethernet (TSE) 10/100/1000 Mbps MAC • USB 2.0 High Speed On-The-Go (OTG) Controller with ULPI Interface • CAN Controller, 2.0B Compliant, Conforms to ISO11898-1, 32 Transmit and 32 Receive Buffers • Two Each: SPI, I2C, Multi-Mode UARTs (MMUART) Peripherals • Hardware Based Watchdog Timer • 1 General Purpose 64-Bit (or two 32-bit) Timer(s) • Real-Time Calendar/Counter (RTC) • DDR Bridge (4 Port Data R/W Buffering Bridge to DDR Memory) with 64-Bit AXI Interface • Non-Blocking, Multi-Layer AHB Bus Matrix Allowing Multi-Master Scheme Supporting 10 Masters and 7 Slaves • Two AHB/APB Interfaces to FPGA Fabric (master/slave capable) • Two DMA Controllers to Offload Data Transactions from the Cortex-M3 Processor – 8-Channel Peripheral DMA (PDMA) for Data Transfer Between MSS Peripherals and Memory – High Performance DMA (HPDMA) for Data Transfer Between eSRAM and DDR Memories Clocking Resources • Clock Sources – Up to Two High Precision 32 KHz to 20 MHz Main Crystal Oscillator – 1 MHz Embedded RC Oscillator – 50 MHz Embedded RC Oscillator • Up to 8 Clock Conditioning Circuits (CCCs) with Up to 8 Integrated Analog PLLs – Output Clock with 8 Output Phases and 45° Phase Difference (Multiply/Divide, and Delay Capabilities) – Frequency: Input 1 to 200 MHz, Output 20 to 400 MHz High Speed Serial Interfaces • Up to 16 SERDES Lanes, Each Supporting: – XGXS/XAUI Extension (to implement a 10 Gbps (XGMII) Ethernet PHY interface) – Native SERDES Interface Facilitates Implementation of Serial RapidIO in Fabric or an SGMII Interface to the Ethernet MAC in MSS – PCI Express (PCIe) Endpoint Controller x1, x2, x4 Lane PCI Express Core with 16-bit PIPE Interface (Gen1/Gen2) 256 Bytes Maximum Payload Size 64-/32-Bit AXI/AHB Master and Slave Interfaces to the Application Layer High Speed Memory Interfaces • Up to 2 High Speed DDRx Memory Controllers – MSS DDR (MDDR) and Fabric DDR (FDDR) Controllers – Supports LPDDR/DDR2/DDR3 – Maximum 333 MHz Clock Rate – SECDED Enable/Disable Feature – Supports Various DRAM Bus Width Modes, x16, x18, x32, x36 – Supports Command Reordering to Optimize Memory Efficiency – Supports Data Reordering, Returning Critical Word First for Each Command • SDRAM Support Operating Voltage and I/Os • 1.2 V Core Voltage • Multi-Standard User I/Os (MSIO/MSIOD) – LVTTL/LVCMOS 3.3 V – LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V – DDR (SSTL2_1, SSTL2_2) – DDR2 (SSTL18_1, SSTL18_2) – LVDS, MLVDS, Mini-LVDS, RSDS Differential Standards –PCI – LVPECL (receiver only) • DDR I/Os (DDRIO) – DDR, DDR2, DDR3, LPDDR, SSTL2, SSTL18, HSTL – LVCMOS 1.2V, 1.5V, 1.8V, 2.5V |
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