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PCA9622 Datasheet(PDF) 6 Page - NXP Semiconductors |
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PCA9622 Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 39 page PCA9622 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 — 6 September 2012 6 of 39 NXP Semiconductors PCA9622 16-bit Fm+ I2C-bus 100 mA 40 V LED driver • ‘reserved for future use’ I2C-bus addresses (0000 011, 1111 1XX) • slave devices that use the 10-bit addressing scheme (1111 0XX) • slave devices that are designed to respond to the General Call address (0000 000) • High-speed mode (Hs-mode) master code (0000 1XX) The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 7.1.2 LED All Call I2C-bus address • Default power-up value (ALLCALLADR register): E0h or 1110 000 • Programmable through I2C-bus (volatile programming) • At power-up, LED All Call I2C-bus address is enabled. PCA9622 sends an ACK when E0h (R/W = 0) or E1h (R/W = 1) is sent by the master. See Section 7.3.8 “ALLCALLADR, LED All Call I2C-bus address” for more detail. Remark: The default LED All Call I2C-bus address (E0h or 1110 000) must not be used as a regular I2C-bus slave address since this address is enabled at power-up. All the PCA9622s on the I2C-bus will acknowledge the address if sent by the I2C-bus master. 7.1.3 LED Sub Call I2C-bus addresses • 3 different I2C-bus addresses can be used • Default power-up values: – SUBADR1 register: E2h or 1110 001 – SUBADR2 register: E4h or 1110 010 – SUBADR3 register: E8h or 1110 100 • Programmable through I2C-bus (volatile programming) • At power-up, Sub Call I2C-bus addresses are disabled. PCA9622 does not send an ACK when E2h (R/W =0) or E3h (R/W = 1), E4h (R/W = 0) or E5h (R/W =1), or E8h (R/W = 0) or E9h (R/W = 1) is sent by the master. See Section 7.3.7 “SUBADR1 to SUBADR3, I2C-bus subaddress 1 to 3” for more detail. Remark: The default LED Sub Call I2C-bus addresses may be used as regular I2C-bus slave addresses as long as they are disabled. Fig 3. Slave address R/W 002aab319 A6 A5 A4 A3 A2 A1 A0 hardware selectable slave address |
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