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M2S120S-VF144Y Datasheet(PDF) 4 Page - Microsemi Corporation |
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M2S120S-VF144Y Datasheet(HTML) 4 Page - Microsemi Corporation |
4 / 156 page SmartFusion2 System-on-Chip FPGAs IV Re vis i on 0 I/Os Per Package Table 1 • SmartFusion2 SoC FPGA Product Family Features M2S005 M2S010 M2S025 M2S050 M2S080 M2S120 Logic Modules (4-Input LUT) 4,956 9,744 23,988 48,672 82,232 120,348 LSRAM 18K Blocks 10 21 31 69 160 236 uSRAM 1K Blocks 11 22 34 72 160 240 Total RAM (Bits) 191K 400K 592K 1,314K 3,040K 4,500K Math Blocks 11 22 34 72 160 240 PLLs and CCCs 22 4 6 8 8 Cortex-M3 Processor + Instruction Cache Yes Yes Yes Yes Yes Yes eNVM (Bytes) 128K 256K 256K 256K 512K 512K eSRAM (Bytes) 64K 64K 64K 64K 64K 64K eSRAM (Bytes non-SECDED) 80K 80K 80K 80K 80K 80K CAN 2.0 A and B 11 1 1 1 1 Triple speed Ethernet 10/100/1000 11 1 1 1 1 USB 2.0 High Speed On-The-Go 11 1 1 1 1 Multi-Mode UART 22 2 2 2 2 SPI 22 2 2 2 2 I2C 22 2 2 2 2 Timer 22 2 2 2 2 DDR Controllers 1x18 1x18 1x18 2x36 2x36 2x36 SERDES Channels 0 4 4 8 8 16 PCIe Endpoint × 4 0 1 1 2 2 4 3.3 V Multi-Standard User I/Os (MSIOs) 123 123 159 139 292 292 MSIOD I/Os 28 40 40 62 106 106 DDRIO I/Os 66 70 90 176 176 176 Total User I/Os 217 233 289 377 574 574 SERDES I/Os 0 16 16 32 64 64 Total User I/Os + SERDES I/Os 217 249 305 409 638 638 Table 2 • I/Os per Package and Package Options Package Options VF400 FG484 FG896 FC1152 Pin Count 400 484 896 1,152 Ball Pitch (mm) 0.8 1.0 1.0 1.0 Length × Width (mm\mm) 17 × 17 23 × 23 31 × 31 35 × 35 I/Os XCVRs I/Os XCVRs I/Os XCVRs I/Os XCVRs M2S005 160 – 217 – – – – – M2S010 160 4 233 4 – – – – M2S025 160 4 267 4 – – – – M2S050 160 4 267 4 377 8 – – M2S080 – – – – – – 574 8 M2S120 – – – – – – 574 16 Note: User I/Os do not include the SERDES and JTAG pins. |
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Similar Description - M2S120S-VF144Y |
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