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CXK581000AYM-55SL Datasheet(PDF) 5 Page - Sony Corporation |
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CXK581000AYM-55SL Datasheet(HTML) 5 Page - Sony Corporation |
5 / 12 page – 5 – CXK581000ATM/AYM/AM/AP — 55 55 55 30 — — — 25 25 • Read cycle (WE = "H") Read cycle time Address access time Chip enable access time (CE1) Chip enable access time (CE2) Output enable to output valid Output hold from address change Chip enable to output in low Z (CE1, CE2) Output enable to output in low Z (OE) Chip disable to output in high Z (CE1, CE2) Output disable to output in high Z (OE) Item Symbol -55LL/55SL -70LL/70SL -10LL/10SL Unit Min. Max. Min. Max. Min. Max. Item Symbol -55LL/55SL -70LL/70SL -10LL/10SL Unit Min. Max. Min. Max. Min. Max. tRC tAA tCO1 tCO2 tOE tOH tLZ1, tLZ2 tOLZ tHZ1, tHZ2∗ tOHZ∗ 55 — — — — 15 10 5 — — 70 — — — — 15 10 5 — — — 70 70 70 40 — — — 25 25 — 100 100 100 50 — — — 35 35 100 — — — — 15 10 5 — — ns ∗ t HZ1 , tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. • Write cycle Write cycle time Address valid to end of write Chip enable to end of write Data to write time overlap Data hold from write time Write pulse width Address setup time Write recovery time (WE) Write recovery time (CE1, CE2) Output active from end of write Write to output in high Z tWC tAW tCW tDW tDH tWP tAS tWR tWR1 tOW tWHZ∗ 55 50 50 25 0 40 0 0 0 10 — — — — — — — — — — — 25 70 60 60 30 0 50 0 0 0 10 — — — — — — — — — — — 25 — — — — — — — — — — 30 100 70 70 40 0 70 0 0 0 10 — ns ∗ t WHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage level. |
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