ISL6377

7

FN8336.0

August 6, 2012

15

ISEN1

Individual current sensing for Channel 1 of the Core VR. If ISEN2 is tied to +5V, this pin cannot be left

open and must be tied to GND with a 10kΩ resistor. If ISEN1 is tied to +5V, the Core portion of the IC is

shut down.

16

ISUMP

Non-inverting input of the transconductance amplifier for current monitor and load line of Core output.

17

ISUMN

Inverting input of the transconductance amplifier for current monitor and load line of Core output.

18

VSEN

Output voltage sense pin for the Core controller. Connect to the +sense pin of the microprocessor die.

19

RTN

Output voltage sense return pin for both Core VR and Northbridge VR. Connect to the -sense pin of the

microprocessor die.

20

IMON

Core output current monitor. A current proportional to the Core VR output current is sourced from this pin.

21

FB

Output voltage feedback to the inverting input of the Core controller error amplifier.

22

COMP

Core controller error amplifier output. A resistor from COMP to GND sets the Core VR offset voltage.

23

PGOOD

Open-drain output to indicate the Core portion of the IC is ready to supply regulated voltage. Pull up

externally to VDD or 3.3V through a resistor.

24

BOOT1

Connect an MLCC capacitor across the BOOT1 and the PHASE1 pins. The boot capacitor is charged,

through an internal boot diode connected from the VDDP pin to the BOOT1 pin, each time the PHASE1

pin drops below VDDP minus the voltage dropped across the internal boot diode.

25

UGATE1

Output of the Phase 1 high-side MOSFET gate driver of the Core VR. Connect the UGATE1 pin to the gate

of the Phase 1 high-side MOSFET(s).

26

PHASE1

Current return path for the Phase 1 high-side MOSFET gate driver of VR1. Connect the PHASE1 pin to the

node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output inductor of

Phase 1.

27

LGATE1

Output of the Phase 1 low-side MOSFET gate driver of the Core VR. Connect the LGATE1 pin to the gate

of the Phase 1 low-side MOSFET(s).

28

PWM_Y

Floating PWM output used for either Channel 3 of the Core VR or Channel 1 of the Northbridge VR

depending on the FCCM_NB resistor connected between FCCM_NB and GND.

29

VDD

5V bias power. A resistor [2Ω] and a decoupling capacitor should be used from the +5V supply. A high

quality, X7R dielectric MLCC capacitor is recommended.

30

VDDP

Input voltage bias for the internal gate drivers. Connect +5V to the VDDP pin. Decouple with at least 1µF

of capacitance to GND. A high quality, X7R dielectric MLCC capacitor is recommended.

31

LGATE2

Output of the Phase 2 low-side MOSFET gate driver of the Core VR. Connect the LGATE2 pin to the gate

of the Phase 2 low-side MOSFET(s).

32

PHASE2

Current return path for the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the PHASE2

pin to the node consisting of the high-side MOSFET source, the low-side MOSFET drain, and the output

inductor of Phase 2.

33

UGATE2

Output of the Phase 2 high-side MOSFET gate driver of the Core VR. Connect the UGATE2 pin to the gate

of the Phase 2 high-side MOSFET(s).

34

BOOT2

Connect an MLCC capacitor across the BOOT2 and PHASE2 pins. The boot capacitor is charged, through

an internal boot diode connected from the VDDP pin to the BOOT2 pin, each time the PHASE2 pin drops

below VDDP minus the voltage dropped across the internal boot diode.

35

PWM4

PWM output of Channel 4 of the Core VR. Disabled if ISEN4 is tied to +5V.

36

BOOTX

Boot connection of the programmable internal driver used for either Channel 3 of the Core VR or

Channel 1 of the Northbridge VR based on the configuration state selected by the FCCM_NB resistor.

Connect an MLCC capacitor across the BOOT1X and the PHASEX pins. The boot capacitor is charged,

through an internal boot diode connected from the VDDP pin to the BOOTX pin, each time the PHASEX

pin drops below VDDP minus the voltage dropped across the internal boot diode.

37

UGATEX

High-side MOSFET gate driver portion of the programmable internal driver used for either Channel 3 of

the Core VR or Channel 1 of the Northbridge VR based on the configuration state selected by the

FCCM_NB resistor. Connect the UGATEX pin to the gate of the high-side MOSFET(s) for either Phase 3 of

the Core VR or Phase 1 of the Northbridge VR based on the configuration state selected.

PIN NUMBER

SYMBOL

DESCRIPTION