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CXP86548 Datasheet(PDF) 9 Page - Sony Corporation |
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CXP86548 Datasheet(HTML) 9 Page - Sony Corporation |
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9 / 24 page  – 9 – CXP86540/86548/86560 Port D data Port D direction IP RD (Port D) Data bus INT2, SI, HS0, HS1, RMC, EC “0” when reset Schmitt input ∗ Large current 12mA ∗ Port D data Port D direction IP RD (Port D) Data bus “0” when reset Schmitt input only for PD1 SCK, SO SIO output enable SCK only ∗ Large current 12mA ∗ Port E data “1” when reset TO ADJ16K∗1 ADJ2K∗1 01 00 10 11 MPX Data bus Port E direction “1” when reset Port E function selection (Lower) “00” when reset IP Port E function selection (Upper) Internal reset signal ∗2 ∗1 ADJ signals are frequency dividing outputs for 32kHz oscillation frequency adjustment. ADJ2K provides usage as buzzer output. ∗2 Pull-up resistors approx. 150k Ω RD (Port E) Port D Port D Port E 6 pins 2 pins 1 pin Hi-Z Hi-Z High level (with approximately 150k Ω resistor when reset) Pin When reset Circuit format PD1/SCK PD2/SO PE0/TO/ADJ PD0/INT2 PD3/SI PD4/HS0 PD5/HS1 PD6/RMC PD7/EC |
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Similar Description - CXP86548 |
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